DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 11

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

■
• Max. of 4 channels can be used
• Dual-address or single-address
• Supports Single, Burst, Sequential,
• Data can be transferred in word
• Activation: internal interrupt,
■
• Max. of 85 channels can be used
• Multiple transfers or multiple
• Supports Single, Burst, Chain and
• Data can be transferred in byte or
• Activation sources: interrupt and
■
• Max. of 4 channels can be used
• Selection of byte or word transfer
• Transfer data in parallel with CPU
• Dual-address or single-address
• Supports Single, Burst, Sequential,
• Data can be transferred in word
• Activation: internal interrupt,
mode can be selected
Idle and Repeat Transfer modes
or byte units
external request, auto-request
types of transfers possible for
one activation source
Repeat Transfer modes
word units
software
data length
or other internal bus master
mode can be selected
Idle and Repeat Transfer modes
or byte units
external request, auto-request
DMA Controller (DMAC)
Data Transfer Controller (DTC)
External DMA Controller
(ExDMAC)
DMA Controller Block Diagram
Data Transfer Controller: Chain Transfer Mode
ExDMA Controller Block Diagram
H8S/2633
HWR, LWR
A23 to A0
DACK
Interrupt
request
RD
(Parallel read and write)
Single-Address Mode
D15 to D0
controller
Interrupt
Data flow
Address bus
EXDMAC
DTC
service
request
(Read)
(Write)
EDREQ
EDACK
External
address bus
On-chip 1KB RAM
Channel n
n + 1
n + 2
H8S/2633
External
data bus
HWR, LWR
BUFFER
A23 to A0
A15 to A0
H8 Peripherals
RD
(Two-cycle read and write)
Dual-Address Mode
D15 to D0
External device
Source
Memory data
Destination
DMA Register
Source
Serial I/O
Destination
Memory
Address bus
with DACK
Address bus
External
memory
Write (2nd cycle)
Read (1st cycle)