DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet
DF3052BX25V
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DF3052BX25V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8/3052B F-ZTAT 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition The list of revisions is a summary of points that ...
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The H8/3052BF is a group of high-performance microcontrollers that integrate system supporting functions together with an H8/300H CPU core. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for ...
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Rev. 3.00 Mar 21, 2006 page vi of xxviii ...
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Main Revisions for this Edition Item Page All 1.1 Overview 5 Table 1.1 Features 1.2 Block Diagram 6 Figure 1.1 Block Diagram 1.3.1 Pin Arrangement 7 Figure 1.2 Pin Arrangement (FP-100B or TFP-100B, Top View) 1.3.2 Pin Assignments in 8, ...
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Item Page 1.3.3 Pin Functions 13, 17 Table 1.3 Pin Functions 6.3.6 Interconnections 138 with Memory (Example) Figure 6.18 Interconnections with Memory (Example) 7.3.4 Interval Timer 176 8.4.4 Repeat Mode 214 Table 8.8 Register Functions in Repeat Mode Rev. 3.00 ...
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Item Page 9.1 Overview 247 Table 9.1 Port Functions 9.11.3 Pin Functions 287 Table 9.19 Port A Pin Functions 13.3.3 Multiprocessor 479 Communication Figure 13.13 Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) 13.3.4 ...
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Item Page 14.3.4 Register Settings 506 Table 14.3 Register Settings in Smart Card Interface 18.8.2 Software 593 Protection Table 18.11 Software Protection 18.7.3 Notes on 587 Program/Program-Verify Procedure Table 18.9 Additional- Programming Data Computation Table 18.10.1 Socket Adapters 600 and ...
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Item Page 20.4.3 Selection of 625 Waiting Time for Exit from Software Standby Mode Table 20.3 Clock Frequency and Waiting Time for Clock to Settle Section 21 Electrical 631 to 658 “Preliminary” deleted Characteristics 21.1 Absolute Maximum 631 Ratings Table ...
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Item Page 21.2.2 AC Characteristics 639 Table 21.7 Timing of On- Chip Supporting Modules 21.2.3 A/D Conversion 640 Characteristics Table 21.8 A/D Converter Characteristics 21.2.4 D/A Conversion 641 Characteristics Table 21.9 D/A Converter Characteristics 21.2.5 Flash Memory 642, 643 Characteristics ...
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Item Page E.2 Timing of Recovery 807 from Hardware Standby Mode Figure E.1 Timing of Recovery from Hardware Standby Mode (2) Appendix F Product 808 Code Lineup Table F.1 H8/3052B F- ZTAT Product Code Lineup Appendix G Package 813 Dimensions ...
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Rev. 3.00 Mar 21, 2006 page xiv of xxviii ...
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Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Block Diagram .................................................................................................................. 1.3 Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Assignments in Each Mode ........................................................................... 1.3.3 Pin Functions ....................................................................................................... 13 Section 2 CPU ...................................................................................................................... 19 2.1 Overview........................................................................................................................... 19 2.1.1 Features................................................................................................................ 19 ...
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Reset State............................................................................................................ 55 2.8.7 Power-Down State ............................................................................................... 55 2.9 Basic Operational Timing ................................................................................................. 56 2.9.1 Overview.............................................................................................................. 56 2.9.2 On-Chip Memory Access Timing........................................................................ 56 2.9.3 On-Chip Supporting Module Access Timing....................................................... 57 2.9.4 Access to External Address Space ....................................................................... 58 Section ...
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Section 5 Interrupt Controller 5.1 Overview........................................................................................................................... 79 5.1.1 Features................................................................................................................ 79 5.1.2 Block Diagram ..................................................................................................... 80 5.1.3 Pin Configuration................................................................................................. 81 5.1.4 Register Configuration......................................................................................... 81 5.2 Register Descriptions ........................................................................................................ 82 5.2.1 System Control Register (SYSCR) ...................................................................... 82 5.2.2 Interrupt Priority Registers A ...
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Operation........................................................................................................................... 119 6.3.1 Area Division ....................................................................................................... 119 6.3.2 Chip Select Signals .............................................................................................. 121 6.3.3 Data Bus............................................................................................................... 122 6.3.4 Bus Control Signal Timing .................................................................................. 123 6.3.5 Wait Modes.......................................................................................................... 131 6.3.6 Interconnections with Memory (Example) .......................................................... 137 6.3.7 Bus Arbiter Operation.......................................................................................... ...
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Register Descriptions (Short Address Mode).................................................................... 191 8.2.1 Memory Address Registers (MAR) ..................................................................... 192 8.2.2 I/O Address Registers (IOAR) ............................................................................. 193 8.2.3 Execute Transfer Count Registers (ETCR).......................................................... 194 8.2.4 Data Transfer Control Registers (DTCR) ............................................................ 195 8.3 Register Descriptions (Full ...
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Register Configuration......................................................................................... 250 9.3 Port 2................................................................................................................................. 252 9.3.1 Overview.............................................................................................................. 252 9.3.2 Register Configuration......................................................................................... 253 9.4 Port 3................................................................................................................................. 256 9.4.1 Overview.............................................................................................................. 256 9.4.2 Register Configuration......................................................................................... 256 9.5 Port 4................................................................................................................................. 258 9.5.1 Overview.............................................................................................................. 258 9.5.2 Register Configuration......................................................................................... 259 9.6 Port 5................................................................................................................................. ...
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Register Descriptions ........................................................................................................ 315 10.2.1 Timer Start Register (TSTR)................................................................................ 315 10.2.2 Timer Synchro Register (TSNC) ......................................................................... 316 10.2.3 Timer Mode Register (TMDR) ............................................................................ 318 10.2.4 Timer Function Control Register (TFCR)............................................................ 321 10.2.5 Timer Output Master Enable Register (TOER) ................................................... ...
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Port A Data Direction Register (PADDR) ........................................................... 401 11.2.2 Port A Data Register (PADR) .............................................................................. 401 11.2.3 Port B Data Direction Register (PBDDR) ........................................................... 402 11.2.4 Port B Data Register (PBDR) .............................................................................. 402 11.2.5 Next Data Register A (NDRA) ...
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Features................................................................................................................ 435 13.1.2 Block Diagram ..................................................................................................... 437 13.1.3 Pin Configuration................................................................................................. 438 13.1.4 Register Configuration......................................................................................... 438 13.2 Register Descriptions ........................................................................................................ 439 13.2.1 Receive Shift Register (RSR) .............................................................................. 439 13.2.2 Receive Data Register (RDR) .............................................................................. 439 13.2.3 Transmit Shift Register (TSR) ...
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Section 15 A/D Converter 15.1 Overview........................................................................................................................... 521 15.1.1 Features................................................................................................................ 521 15.1.2 Block Diagram ..................................................................................................... 522 15.1.3 Pin Configuration................................................................................................. 523 15.1.4 Register Configuration......................................................................................... 524 15.2 Register Descriptions ........................................................................................................ 525 15.2.1 A/D Data Registers (ADDRA to ADDRD).............................................. 525 15.2.2 ...
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Features ............................................................................................................................. 555 18.2 Overview........................................................................................................................... 556 18.2.1 Block Diagram ..................................................................................................... 556 18.2.2 Mode Transitions ................................................................................................. 556 18.2.3 On-Board Programming Modes........................................................................... 559 18.2.4 Flash Memory Emulation in RAM ...................................................................... 561 18.2.5 Differences between Boot Mode and User Program Mode ................................. ...
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Connecting a Crystal Resonator........................................................................... 609 19.2.2 External Clock Input ............................................................................................ 611 19.3 Duty Adjustment Circuit ................................................................................................... 613 19.4 Prescalers .......................................................................................................................... 613 19.5 Frequency Divider............................................................................................................. 613 19.5.1 Register Configuration......................................................................................... 614 19.5.2 Division Control Register (DIVCR) .................................................................... 614 19.5.3 Usage Notes ...
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Flash Memory Characteristics.............................................................................. 642 21.3 Operational Timing ........................................................................................................... 643 21.3.1 Bus Timing .......................................................................................................... 643 21.3.2 Refresh Controller Bus Timing............................................................................ 647 21.3.3 Control Signal Timing ......................................................................................... 652 21.3.4 Clock Timing ....................................................................................................... 654 21.3.5 TPC and I/O Port Timing..................................................................................... 654 21.3.6 ...
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E.2 Timing of Recovery from Hardware Standby Mode......................................................... 807 Appendix F Product Code Lineup Appendix G Package Dimensions Appendix H Differences from H8/3048F-ZTAT Rev. 3.00 Mar 21, 2006 page xxviii of xxviii .................................................................................. 808 .................................................................................. 809 ....................................................... 811 ...
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Overview The H8/3052BF is a group of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Renesas Technology architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, ...
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Section 1 Overview Table 1.1 Features Feature Description CPU Upward-compatible with the H8/300 CPU at the object-code level General-register machine Sixteen 16-bit general registers (also usable as + eight 16-bit registers or eight 32-bit registers) High-speed operation Maximum clock rate: ...
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Feature Description Bus controller Address space can be partitioned into eight areas, with independent bus specifications in each area Chip select output available for areas 8-bit access or 16-bit access selectable for each area Two-state or three-state ...
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Section 1 Overview Feature Description 16-bit integrated Five 16-bit timer channels, capable of processing pulse outputs or timer unit (ITU) 10 pulse inputs 16-bit timer counter (channels Two multiplexed output compare/input capture pins (channels ...
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Feature Description D/A converter Resolution: 8 bits Two channels D/A outputs can be sustained in software standby mode I/O ports 70 input/output pins 9 input-only pins Operating Seven MCU operating modes modes Mode Mode 1 Mode 2 Mode 3 Mode ...
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Section 1 Overview 1.2 Block Diagram Figure 1.1 shows an internal block diagram EXTAL XTAL STBY RES FWE NMI P6 /LWR 6 P6 /HWR /BACK 2 ...
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Pin Description 1.3.1 Pin Arrangement Figure 1.2 shows the pin arrangement of the H8/3052BF REF ...
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Section 1 Overview 1.3.2 Pin Assignments in Each Mode Table 1.2 lists the pin assignments in each mode. Table 1.2 Pin Assignments in Each Mode (FP-100B or TFP-100B) Pin No. Mode 1 Mode ...
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Pin No. Mode 1 Mode ...
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Section 1 Overview Pin No. Mode 1 Mode ...
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Pin No. Mode 1 Mode REF REF 78 P7 / / /AN P7 /AN 2 ...
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Section 1 Overview Pin No. Mode 1 Mode / / TIOCB / TIOCB 0 0 TCLKD TCLKD TIOCA / TIOCA 1 ...
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Pin Functions Table 1.3 summarizes the pin functions. Table 1.3 Pin Functions Type Symbol Power Clock XTAL EXTAL Operating mode control Pin No. I/O Name and Function 35, ...
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Section 1 Overview Type Symbol RES System control FWE STBY BREQ BACK Interrupts NMI IRQ to IRQ 5 0 Address bus Data bus Bus control 7 0 ...
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Type Symbol RFSH Refresh controller HWR LWR DREQ DMA controller , 1 DREQ (DMAC) 0 TEND , 1 TEND 0 16-bit integrated TCLKD to timer unit (ITU) TCLKA TIOCA to 4 TIOCA 0 TIOCB to 4 TIOCB ...
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Section 1 Overview Type Symbol Programmable timing pattern controller (TPC) Serial TxD , TxD 1 0 communication interface (SCI) RxD , RxD 1 0 SCK , SCK 1 0 A/D converter ...
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Type Symbol I/O ports Pin ...
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Section 1 Overview Rev. 3.00 Mar 21, 2006 page 18 of 814 REJ09B0302-0300 ...
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Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 2 CPU 16 16-bit register-register multiply: 32 ÷ 16-bit register-register divide: Two CPU operating modes Normal mode (not available in the H8/3052BF) Advanced mode Low-power mode Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 CPU In ...
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CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports Mbytes. The H8/3052BF can be used only in advanced mode. (Information from ...
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Section 2 CPU 2.3 Address Space The maximum address space of the H8/300H CPU is 16 Mbytes. The H8/3052BF has various operating modes (MCU modes), some providing a 1-Mbyte address space, the others supporting the full 16 Mbytes. Figure 2.2 ...
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Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 Control ...
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Section 2 CPU 2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as ...
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General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack. SP (ER7) 2.4.3 Control Registers The control registers are ...
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Section 2 CPU carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set there is a carry or borrow at bit ...
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Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
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Section 2 CPU General Data Type Register Data Format Word data Rn 15 Word data En MSB 31 Longword data ERn MSB Legend: ERn: General register En: General register E Rn: General register R RnH: General register RH RnL: General ...
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Memory Data Formats Figure 2.7 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address attempt is made ...
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Section 2 CPU 2.6 Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified in table 2.1. Table 2.1 Instruction Classification Function Instruction MOV, PUSH * Data transfer Arithmetic operations ADD, SUB, ADDX, ...
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Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Function Instruction Data MOV BWL transfer POP, PUSH — MOVFPE * , — MOVTPE * Arithmetic ADD, CMP BWL ...
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Section 2 CPU 2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination General register ...
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Table 2.3 Data Transfer Instructions Size * Instruction MOV B/W/L MOVFPE B MOVTPE B POP W/L PUSH W/L Note: * Size refers to the operand size. B: Byte W: Word L: Longword Function (EAs) Rd, Rs (EAd) Moves data between ...
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Section 2 CPU Table 2.4 Arithmetic Operation Instructions Size * Instruction ADD, SUB B/W/L ADDX, SUBX B INC, DEC B/W/L ADDS, SUBS L DAA, DAS B MULXU B/W MULXS B/W Rev. 3.00 Mar 21, 2006 page 34 of 814 REJ09B0302-0300 ...
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Size * Instruction DIVXU B/W DIVXS B/W CMP B/W/L NEG B/W/L EXTS W/L EXTU W/L Note: * Size refers to the operand size. B: Byte W: Word L: Longword Function Rd ÷ Performs unsigned division on data in ...
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Section 2 CPU Table 2.5 Logic Operation Instructions Size * Instruction AND B/W/L OR B/W/L XOR B/W/L NOT B/W/L Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Shift Instructions Size * Instruction ...
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Table 2.7 Bit Manipulation Instructions Size * Instruction BSET B BCLR B BNOT B BTST B BAND B BIAND B Function 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit ...
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Section 2 CPU Size * Instruction BOR B BIOR B BXOR B BIXOR B BLD B BILD B BST B BIST B Note: * Size refers to the operand size. B: Byte Rev. 3.00 Mar 21, 2006 page 38 of ...
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Table 2.8 Branching Instructions Instruction Size Bcc — JMP — BSR — JSR — RTS — Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description BRA (BT) Always (true) ...
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Section 2 CPU Table 2.9 System Control Instructions Size * Instruction TRAPA — RTE — SLEEP — LDC B/W STC B/W ANDC B ORC B XORC B NOP — Note: * Size refers to the operand size. B: Byte W: ...
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Table 2.10 Block Transfer Instruction Instruction Size EEPMOV.B — EEPMOV.W — Function if R4L 0 then repeat @ER5+ @ER6+, R4L – 1 until R4L = 0 else next then repeat @ER5+ @ER6+, R4 – 1 until R4 ...
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Section 2 CPU 2.6.4 Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc). ...
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Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these instructions are used ...
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Section 2 CPU Explanation of BCLR Instruction To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write- only register read as H'FF, even though its true value is H'3F. Next the CPU ...
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Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers and can ...
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Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address 1-Mbyte Modes 8 bits (@aa:8) H'FFF00 to H'FFFFF (1048320 to 1048575) 16 bits (@aa:16) H'00000 to H'07FFF, H'F8000 to H'FFFFF (0 to 32767, 1015808 to 1048575) 24 bits (@aa:24) ...
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Specified by @aa:8 Figure 2.9 Memory-Indirect Branch Address Specification When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. ...
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Section 2 CPU Table 2.13 Effective Address Calculation Addressing Mode and No. Instruction Format 1 Register direct (Rn Register indirect (@ERn Register indirect with displacement @(d:16, ERn)/@(d:24, ERn disp 4 Register ...
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Addressing Mode and Instruction Format No. 5 Absolute address @aa:8 op abs @aa:16 op abs @aa:24 op abs 6 Immediate #xx:8, #xx:16, or #xx:32 op IMM 7 Program-counter relative @(d:8, PC) or @(d:16, PC) op disp Effective Address Calculation 0 ...
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Section 2 CPU Addressing Mode and Instruction Format No. 8 Memory indirect @@aa:8 · Normal mode op abs · Advanced mode op abs Legend: r, rm, rn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: Absolute address ...
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Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.10 ...
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Section 2 CPU 2.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to ...
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Reset Exception Interrupt sources Trap instruction Figure 2.11 Classification of Exception Sources End of bus release Bus request Bus-released state End of exception handling Exception-handling state RES = High STBY = High, *1 Reset state Notes: 1. From any state ...
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Section 2 CPU 2.8.4 Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. ...
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Bus-Released State In this state the bus is released to a bus master other than the CPU, in response to a bus request. The bus masters other than the CPU are the DMA controller, the refresh controller, and an ...
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Section 2 CPU 2.9 Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock ( ). The interval from one rise of the system clock to the next rise is referred “state.” A ...
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Address bus HWR LWR , , Figure 2.15 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus ...
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Section 2 CPU Address bus HWR LWR , , Figure 2.17 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8/3052BF has seven operating modes (modes that are selected by the mode pins ( indicated in table 3.1. The input at ...
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Section 3 MCU Operating Modes Modes 5 and 6 are externally expanded modes that enable access to external memory and peripheral devices and also enable access to the on-chip ROM. Mode 5 supports a maximum address space of 1 Mbyte. ...
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Bits 2 to 0—Mode Select (MDS2 to MDS0): These bits indicate the logic levels at pins (the current operating mode). MDS2 to MDS0 correspond MDS0 are read-only bits. The mode ...
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Section 3 MCU Operating Modes Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is ...
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Operating Mode Descriptions 3.4.1 Mode 1 Ports 1, 2, and 5 function as address pins A address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas least one area ...
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Section 3 MCU Operating Modes 3.4.6 Mode 6 Ports 1, 2, and 5 and part of port A function as address pins A maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2, ...
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Memory Map in Each Operating Mode Figure 3.1 shows a memory map of the H8/3052BF. The address space is divided into eight areas. The initial bus mode differs between modes 1 and 2, and also between modes 3 and ...
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Section 3 MCU Operating Modes Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'F8000 H'FDF0F ...
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Mode 5 (1-Mbyte expanded mode with on-chip ROM enabled) H'00000 Vector area H'000FF On-chip ROM H'07FFF Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 Area 3 H'7FFFF H'80000 External address Area 4 space H'9FFFF H'A0000 Area ...
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Section 3 MCU Operating Modes Rev. 3.00 Mar 21, 2006 page 68 of 814 REJ09B0302-0300 ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.1.3 Exception Sources and Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset ...
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Table 4.2 Exception Vector Table Exception Source Reset Reserved for system use External interrupt (NMI) Trap instruction (4 sources) External interrupt IRQ 0 External interrupt IRQ 1 External interrupt IRQ 2 External interrupt IRQ 3 External interrupt IRQ 4 External ...
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Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and ...
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Figure 4.2 Reset Sequence (Modes 1 and 3) Section 4 Exception Handling Rev. 3.00 Mar 21, 2006 page 73 of 814 REJ09B0302-0300 ...
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Section 4 Exception Handling RES Address bus RD HWR LWR , High (1), (3) Address of reset vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset vector) (5) Start address ...
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RES Internal address bus Internal read signal Internal write signal Internal data bus (16 bits wide) (1), (3) Address of reset vector ((1) = H'000000, (2) = H'000002) (2), (4) Start address (contents of reset vector) (5) Start address (6) ...
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Section 4 Exception Handling 4.3 Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ 30 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt sources and indicates the number of interrupts of each ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set the system control register (SYSCR), the exception handling sequence sets the I bit CCR. ...
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Section 4 Exception Handling 4.6 Notes on Use of the Stack When accessing word data or longword data, the H8/3052BF regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a source-by-source or module-by-module basis ...
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Section 5 Interrupt Controller 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR NMI input IRQ input OVF TME . . . . . . . . . . ADI ADIE Interrupt controller Legend: ISCR: ...
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Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Nonmaskable interrupt External interrupt request 5.1.4 Register Configuration Table 5.2 lists the registers of the interrupt controller. Table 5.2 Interrupt Controller Registers Address ...
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Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables ...
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Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3: UE Description 0 UI bit in CCR is used as interrupt mask bit 1 UI ...
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Section 5 Interrupt Controller Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 6 IPRA7 IPRA6 Initial value 0 0 Read/Write R/W R/W Priority level A6 Selects the ...
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Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ Bit 7: IPRA7 Description 0 IRQ interrupt requests have priority level 0 (Non-priority IRQ interrupt requests have priority level 1 (Priority) 0 Bit 6—Priority Level A6 (IPRA6): ...
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Section 5 Interrupt Controller Bit 2—Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests. Bit 2: IPRA2 Description 0 ITU channel 0 interrupt requests have priority level 0 (Non-priority) 1 ITU channel 0 interrupt requests ...
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Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRB7 IPRB6 Initial value 0 Read/Write R/W R/W Priority level B6 Selects the priority level of ITU channel 4 ...
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Section 5 Interrupt Controller Bit 7—Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests. Bit 7: IPRB7 Description 0 ITU channel 3 interrupt requests have priority level 0 (low priority) (Initial value) 1 ITU channel ...
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Bit 1—Priority Level B1 (IPRB1): Selects the priority level of A/D converter interrupt requests. Bit 1: IPRB1 Description 0 A/D converter interrupt requests have priority level 0 (low priority) (Initial value) 1 A/D converter interrupt requests have priority level 1 ...
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Section 5 Interrupt Controller 5.2.4 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ Bit 7 6 — — Initial value 0 0 Read/Write R/W R/W Reserved bits IER is initialized to H'00 by ...
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IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ to IRQ . 5 0 Bit 7 6 — — Initial value 0 0 Read/Write ...
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Section 5 Interrupt Controller 5.3 Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ can be used to exit software standby mode. NMI: NMI is the highest-priority interrupt ...
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Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). IRQn input pin IRQnF Note Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector numbers 12 to 17. ...
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Section 5 Interrupt Controller Table 5.3 Interrupt Sources, Vector Addresses, and Priority Interrupt Source Origin NMI External pins IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 Reserved — WOVI Watchdog (interval timer) timer CMI Refresh (compare ...
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Interrupt Source Origin IMIA2 ITU channel 2 (compare match/ input capture A2) IMIB2 (compare match/ input capture B2) OVI2 (overflow 2) Reserved — IMIA3 ITU channel 3 (compare match/ input capture A3) IMIB3 (compare match/ input capture B3) OVI3 (overflow ...
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Section 5 Interrupt Controller Interrupt Source Origin ERI0 SCI channel 0 (receive error 0) RXI0 (receive data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) ERI1 SCI channel 1 (receive error 1) RXI1 (receive data full 1) ...
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Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3052BF handles interrupts differently depending on the setting of the UE bit. When interrupts are controlled by the I bit. When interrupts are controlled by the ...
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Section 5 Interrupt Controller Priority level 1? No IRQ 0 Yes IRQ Figure 5.4 Process Up to Interrupt Acceptance when Rev. 3.00 Mar 21, 2006 page 98 of 814 REJ09B0302-0300 Program execution state Interrupt requested? Yes Yes ...
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If an interrupt condition occurs and the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. 2. When the interrupt controller receives one or more interrupt requests, it selects the highest- ...
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Section 5 Interrupt Controller a. All interrupts are enabled I 0 Figure 5.5 Interrupt Enable/Disable State Transitions (Example) Figure 5 flowchart showing how interrupts are accepted when interrupt condition occurs and the ...
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Program execution state Interrupt requested? Yes Priority level 1? Yes No IRQ 0 Yes No IRQ 1 Yes ADI Yes Yes Yes Save PC and CCR I Read vector address Branch to interrupt service routine Figure 5.6 ...
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Section 5 Interrupt Controller 5.4.2 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt sequence in mode 2 when the program area and stack area are in 16-bit, two-state access space in external memory. Figure 5.7 Interrupt Sequence (Mode 2, ...
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Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time No. Item 1 Interrupt priority decision ...
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Section 5 Interrupt Controller 5.5 Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an instruction clears an interrupt enable bit disable the interrupt, the interrupt is not actually disabled until after execution of the instruction ...
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Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting ...
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Section 5 Interrupt Controller Occurrence Conditions ISR register read is executed to clear the IRQaF flag while IRQaF = 1, and then the IRQbF flag is cleared by the initiation of interrupt exception handling there ...
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MOV.B @ISR,R0L MOV.B #HFE,R0L MOV.B R0L,@ISR Solution 2 During IRQb interrupt processing, carry out IRQbF flag clear dummy processing. For example IRQB MOV.B #HFD,R0L MOV.B R0L,@ISR · · · Section 5 Interrupt Controller Rev. 3.00 Mar ...
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Section 5 Interrupt Controller Rev. 3.00 Mar 21, 2006 page 108 of 814 REJ09B0302-0300 ...
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Section 6 Bus Controller 6.1 Overview The H8/3052BF has an on-chip bus controller that divides the address space into eight areas and can assign different bus specifications to each. This enables different types of memory to be connected easily. A ...
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Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. Internal address bus Area decoder Chip select control signals WAIT Internal signals CPU bus request signal DMAC bus request signal Refresh controller bus ...
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Pin Configuration Table 6.1 summarizes the bus controller’s input/output pins. Table 6.1 Bus Controller Pins Name Abbreviation Chip select Address strobe RD Read HWR High write LWR Low write WAIT Wait ...
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Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the bus controller’s registers. Table 6.2 Bus Controller Registers Address * Name H'FFEC Bus width control register H'FFED Access state control register H'FFEE Wait control register H'FFEF Wait state controller ...
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Bits 7 to 0—Area Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or 16-bit access to the corresponding address areas. Bits ABW7 to ABW0 Description 0 Areas are ...
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Section 6 Bus Controller 6.2.3 Wait Control Register (WCR) WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. Bit 7 6 — — Initial value 1 ...
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Wait State Controller Enable Register (WCER) WCER is an 8-bit readable/writable register that enables or disables wait-state control of external three-state-access areas by the wait-state controller. Bit 7 6 WCE7 WCE6 Initial value 1 1 Read/Write R/W R/W WCER ...
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Section 6 Bus Controller 6.2.5 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A enables or disables release of the bus to an external device. Bit 7 A23E Initial value ...
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Bit 5—Address 21 Enable (A21E): Enables PA Writing 0 in this bit enables A cannot be modified and PA has its ordinary input/output functions. 6 Bit 5: A21E Description the the PA ...
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Section 6 Bus Controller 6.2.6 Chip Select Control Register (CSCR) CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals chip select signal (CS 7 ...
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Operation 6.3.1 Area Division The external address space is divided into areas Each area has a size of 128 kbytes in the 1-Mbyte modes Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general ...
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Section 6 Bus Controller to CS Chip select signals (CS 7 can be selected in ABWCR, ASTCR, WCER, and WCR as shown in table 6.3. Table 6.3 Bus Specifications ABWCR ASTCR WCER ABWn ASTn WCEn 0 0 — ...
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Chip Select Signals For each of areas the H8/3052BF can output a chip select signal (CS to indicate when the area is selected. Figure 6.3 shows the output timing 0). Output of CS ...
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Section 6 Bus Controller 6.3.3 Data Bus The H8/3052BF allows either 8-bit access or 16-bit access to be designated for each of areas 8-bit-access area uses the upper data bus (D upper data bus (D to ...
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Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6.4 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper address bus (D pin is always high. Wait states can be inserted. Address bus CS n ...
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Section 6 Bus Controller 8-Bit, Two-State-Access Areas: Figure 6.5 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper address bus (D pin is always high. Wait states cannot be inserted. Address bus ...
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Three-State-Access Areas: Figures 6.6 to 6.8 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper address bus (D even addresses and the lower address bus (D can be inserted. Address bus ...
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Section 6 Bus Controller Address bus Read access HWR LWR Write access Note ...
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Address bus Read access HWR LWR Write access Note Figure 6.8 ...
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Section 6 Bus Controller 16-Bit, Two-State-Access Areas: Figures 6.9 to 6.11 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper address bus (D even addresses and the lower address bus (D cannot ...
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Address bus Read access HWR LWR Write access Note Figure 6.10 ...
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Section 6 Bus Controller Address bus Read access HWR LWR Write access Note ...
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Wait Modes Four wait modes can be selected as shown in table 6.5. Table 6.5 Wait Mode Selection ASTCR WCER ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control 0 — — — ...
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Section 6 Bus Controller Wait Mode in Areas Where Wait-State Controller is Disabled: External three-state access areas in which the wait-state controller is disabled (ASTn = 1, WCEn = 0) operate in pin wait mode 0. The other wait modes ...
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Wait Modes in Areas Where Wait-State Controller is Enabled: External three-state access areas in which the wait-state controller is enabled (ASTn = 1, WCEn = 1) can operate in pin wait mode 1, pin auto-wait mode, or programmable wait mode, ...
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Section 6 Bus Controller Pin Auto-Wait Mode If the WAIT pin is low, the number of wait states (T inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock ( ) in ...
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Programmable Wait Mode The number of wait states (T W external three-state-access areas. Figure 6.15 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). Address bus AS RD Read access Data bus HWR, LWR ...
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Section 6 Bus Controller Example of Wait State Control Settings: A reset initializes ASTCR and WCER to H'FF and WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can select other wait modes for ...
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Interconnections with Memory (Example) For each area, the bus controller can select two- or three-state access and 16-bit data bus width. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the ...
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Section 6 Bus Controller H8/3052BF WAIT RD HWR LWR Figure 6.18 Interconnections with Memory (Example) Rev. 3.00 Mar 21, ...
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Bus Arbiter Operation The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are four bus masters: the CPU, DMA controller (DMAC), refresh controller, and an external bus master. When a bus master has ...
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Section 6 Bus Controller DMAC: When the DMAC receives an activation request, it requests the bus right from the bus arbiter. If the DMAC is bus master and the refresh controller or an external bus master requests the bus, the ...
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Figure 6.19 shows the timing when the bus right is requested by an external bus master during a read cycle in a two-state-access area. There is a minimum interval of two states from when the BREQ signal goes low until ...
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Section 6 Bus Controller 6.4 Usage Notes 6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM A different bus control signal timing applies when dynamic RAM or pseudo-static RAM is connected to area 3. For details see section 7, Refresh Controller. ...
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DDR Write Timing: Data written to a data direction register (DDR) to change output to generic input, or vice versa, takes effect starting from the T n cycle. Figure 6.21 shows the timing when the CS Address ...
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Section 6 Bus Controller BREQ Input Timing BREQ BREQ BREQ 6.4.3 After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high level before BACK goes low, the bus arbiter may operate ...
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Section 7 Refresh Controller 7.1 Overview The H8/3052BF has an on-chip refresh controller that enables direct connection of 16-bit-wide DRAM or pseudo-static RAM (PSRAM). DRAM or pseudo-static RAM can be directly connected to area 3 of the external address space. ...
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Section 7 Refresh Controller Features as a Pseudo-Static RAM Refresh Controller RFSH signal output for refresh control Software-selectable refresh interval Software-selectable self-refresh mode Wait states can be inserted Features as an Interval Timer Refresh timer counter (RTCNT) can be used ...
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Block Diagram Figure 7.1 shows a block diagram of the refresh controller. /2, /8, /32, /128, /512, /2048, /4096 Clock selector Comparator Legend: RTCNT: Refresh timer counter RTCOR: Refresh time constant register RTMCSR: Refresh timer control/status register RFSHCR: Refresh ...
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Section 7 Refresh Controller 7.1.3 Pin Configuration Table 7.1 summarizes the refresh controller’s input/output pins. Table 7.1 Refresh Controller Pins Signal Pin Name RFSH Refresh HWR Upper write/upper column address strobe LWR Lower write/lower column address strobe RD Column address ...
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Register Descriptions 7.2.1 Refresh Control Register (RFSHCR) RFSHCR is an 8-bit readable/writable register that selects the operating mode of the refresh controller. Bit 7 6 SRFMD PSRAME Initial value 0 0 Read/Write R/W R/W PSRAM enable and DRAM enable ...
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Section 7 Refresh Controller Bit 7—Self-Refresh Mode (SRFMD): Specifies DRAM or pseudo-static RAM self-refresh during software standby mode. When PSRAME = 1 and DRAME = 0, after the SRFMD bit is set to 1, pseudo-static RAM can be self-refreshed when ...
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Bit 3—Address Multiplex Mode Select (M9/M8 The setting of this bit is valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled when the PSRAME or DRAME bit is set Bit 3: ...
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Section 7 Refresh Controller 7.2.2 Refresh Timer Control/Status Register (RTMCSR) RTMCSR is an 8-bit readable/writable register that selects the clock source for RTCNT. It also enables or disables interrupt requests when the refresh controller is used as an interval timer. ...
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Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt requested when the CMF flag is set RTMCSR. The CMIE bit is always cleared to 0 when PSRAME = 1 or DRAME = 1. Bit ...
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Section 7 Refresh Controller RTCNT is write-disabled when the PSRAME bit or DRAME bit is set to 1. RTCNT is initialized to H' reset and in standby mode. 7.2.4 Refresh Time Constant Register (RTCOR) RTCOR is an 8-bit ...
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Operation 7.3.1 Overview One of three functions can be selected for the H8/3052BF refresh controller: interfacing to DRAM connected to area 3, interfacing to pseudo-static RAM connected to area 3, or interval timing. Table 7.3 summarizes the register settings ...
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Section 7 Refresh Controller DRAM Interface: To set up area 3 for connection to 16-bit-wide DRAM, initialize RTCOR, RTMCSR, and RFSHCR in that order, clearing bit PSRAME to 0 and setting bit DRAME to 1. DDR the ...
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DRAM Refresh Control Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is determined by the settings of RTCOR and bits CKS2 to CKS0 in RTMCSR. Figure 7.2 illustrates the refresh request interval. RTCOR H'00 Refresh request ...
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Section 7 Refresh Controller When a refresh request occurs in the refresh request pending state, the refresh controller acquires the bus right, then executes a refresh cycle. If another refresh request occurs during execution of the refresh cycle ...
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Address Multiplexing: Address multiplexing depends on the setting of the M9/M8 bit in RFSHCR, as described in table 7.5. Figure 7.4 shows the address output timing. Address output is multiplexed only in area 3. Table 7.5 Address Multiplexing Address Pins ...
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Section 7 Refresh Controller CAS and 2WE CAS CAS WE WE Modes: The CAS/WE bit in RFSHCR can select two control modes for 16-bit- WE 2CAS wide DRAM: one using UCAS and LCAS; the other using UW and LW. These ...
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Read cycle Address Row Column bus CS 3 (RAS) HWR (UCAS) HWR (UW) LWR (LW) RFSH AS Note: * 16-bit access Figure 7.5 DRAM Control Signal Output Timing (2) (2CAS Refresh Cycle Priority Order: When there are simultaneous bus requests, ...
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Section 7 Refresh Controller Self-Refresh Mode: Some DRAM devices have a self-refresh function. After the SRFMD bit is set RFSHCR, when a transition to software standby mode occurs, the CAS and RAS outputs go low in that ...
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Address bus CS (RAS (CAS) HWR (UW) High LWR (LW) High RFSH Address bus CS (RAS) 3 HWR (UCAS) LWR (LCAS) RD (WE) RFSH Figure 7.6 Signal Output Timing in Self-Refresh Mode (PSRAME = 0, DRAME = 1) ...
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Section 7 Refresh Controller Operation in Power-Down State: The refresh controller operates in sleep mode. It does not operate in hardware standby mode. In software standby mode RTCNT is initialized, but RFSHCR, RTMCSR bits and RTCOR retain ...
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Set area 3 for 16-bit access Set P8 DDR to 1 for 1 Set bits CKS2 to CKS0 in RTMCSR Write H'23 in RFSHCR Wait for DRAM to be initialized DRAM can be accessed Figure 7.8 Setup Procedure for 2WE ...
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Section 7 Refresh Controller Example 2: Connection to 2WE 4-Mbit DRAM (16-Mbyte Mode): Figure 7.9 shows typical interconnections to a single 2WE 4-Mbit DRAM, and the corresponding address map. Figure 7.10 shows a setup procedure to be followed by a ...
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Figure 7.10 Setup Procedure for 2WE 4-Mbit DRAM with 10-Bit Row Address and 8-Bit Column Address (16-Mbyte Mode) Set area 3 for 16-bit access CS Set P8 DDR to 1 for output 1 3 Set RTCOR Set bits CKS2 to ...
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Section 7 Refresh Controller CAS CAS CAS 4-Mbit DRAM (16-Mbyte Mode): Figure 7.11 shows typical Example 3: Connection to 2CAS interconnections to a single 2CAS 4-Mbit DRAM, and the corresponding address map. Figure 7.12 shows a setup procedure to be ...
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Figure 7.12 Setup Procedure for 2CAS Column Address (16-Mbyte Mode) Set area 3 for 16-bit access CS Set P8 DDR to 1 for output 1 3 Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'3B in RFSHCR Wait ...
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Section 7 Refresh Controller Example 4: Connection to Multiple 4-Mbit DRAM Chips (16-Mbyte Mode): Figure 7.13 shows an example of interconnections to two 2CAS 4-Mbit DRAM chips, and the corresponding address map four DRAM chips can be connected ...