HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 317

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bits 5 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bits 2 to 0—Bit Counter (BC2 to BC0): BC2 to BC0 specify the number of bits to be transferred
next. When the ACK bit is cleared to 0 in ICCR (acknowledgement mode), the data is transferred
with one additional acknowledge bit. BC2 to BC0 settings should be made during an interval
between transfer frames. If BC2 to BC0 are set to a value other than 000, the setting should be
made while the SCL line is low.
The bit counter is initialized to 000 by a reset and when a start condition is detected. The value
returns to 000 at the end of a data transfer, including the acknowledge.
Bit 2:
BC2
0
1
13.2.4
ICCR is an 8-bit readable/writable register that enables or disables the I
disables interrupts, and selects master or slave mode, transmit or receive, acknowledgement or
serial mode, and the clock frequency.
ICCR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—I
When ICE is set to 1, the SCL and SDA signals are assigned to input/output pins and transfer
operations are enabled. When ICE is cleared to 0, SCL and SDA are placed in the high-impedance
state and the interface module is disabled.
Bit
Initial value
Read/Write
2
C Bus Interface Enable (ICE): Selects whether or not to use the I
I
2
Bit 1:
BC1
0
1
0
1
C Bus Control Register (ICCR)
R/W
ICE
7
0
Bit 0:
BC0
0
1
0
1
0
1
0
1
IEIC
R/W
6
0
Serial Mode
8
1
2
3
4
5
6
7
MST
R/W
5
0
TRS
R/W
4
0
Acknowledgement Mode
9
2
3
4
5
6
7
8
Bits/Frame
ACK
R/W
3
0
CKS2
R/W
2
C bus interface, enables or
2
0
2
C bus interface.
CKS1
R/W
1
0
(Initial value)
CKS0
R/W
0
0
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