HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 357

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

14.3.3
The A
computers with an 8086*-family CPU. In slave mode, a regular-speed A
output under software control, or a fast A
A
Note: * Intel microprocessor.
Regular A
command followed by data. When the slave processor receives data, it normally uses an interrupt
routine activated by the IBF1 interrupt to read IDR1. If the data follows an H'D1 command,
software copies bit 1 of the data and outputs it at the gate A
Fast A
A
this pin will be a logic 1, which is the initial DR value. Afterward, the host processor can
manipulate the output from this pin by sending commands and data. This function is available
only when register IDR1 is accessed using CS
host processor. When an H'D1 host command is detected, bit 1 of the data following the host
command is output from the GA
interrupts, and is faster than the regular processing using interrupts. Table 14.6 lists the conditions
that set and clear GA
indicates the GA
Table 14.6 GA
Pin Name
GA20 (P8
20
20
gate output is enabled by setting the FGA20E bit (bit 0) to 1 in HICR (H'FFF0).
gate signal. Bit P8
20
20
gate signal can mask address A
Gate Operation: When the FGA20E bit is set to 1, P8
A
1
)
20
20
Gate Operation: Output of the A
Gate
Setting Condition
Rising edge of the host’s write signal
(IOW) when bit 1 of the written data
is 1 and the data follows an H'D1
host command
20
20
output signal values.
(P8
20
1
DDR must be set to 1 to assign this pin for output. The initial output from
1
(P8
) Set/Clear Timing
1
). Figure 14.2 describes the GA
20
output pin. This operation does not depend on software or
20
20
to emulate an addressing mode used by personal
gate signal can be output under hardware control. Fast
1
. Slave logic decodes the commands input from the
20
gate signal can be controlled by an H'D1
Clearing Condition
Rising edge of the host’s write signal
(IOW) when bit 1 of the written data is 0
and the data follows an H'D1 host
command
20
20
output in flowchart form. Table 14.7
pin (P8
1
/GA
1
20
/GA
is used for output of a fast
20
20
gate signal can be
).
327