HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 355

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.2.2
The bus control register 2 (BCR2) is a 16-bit read/write register that selects the bus-size width of
each area. It is initialized to H'3FF0 by a power-on reset, but is not initialized by a manual reset or
by standby mode. Do not access external memory outside area 0 until BCR2 register initialization
is complete.
Bits 15, 14, 3, 2, 1, and 0—Reserved: These bits are always read as 0. The write value should
always be 0.
Bits 2n + 1, 2n—Area n (2 to 6) Bus Size Specification (AnSZ1, AnSZ0): Specify the bus sizes
of physical space area n (n = 2 to 6).
Bit 2n + 1: AnSZ1
0
1
0
1
Initial value:
R/W:
Bit:
Bus Control Register 2 (BCR2)
15
—
R
0
14
—
R
0
Bit 2n: AnSZ0
0
1
0
1
0
1
0
1
R/W
SZ1
A6
13
1
R/W
SZ0
A6
12
1
R/W
SZ1
A5
11
1
R/W
SZ0
A5
10
1
Port A / B
Unused
Used
R/W
SZ1
A4
9
1
R/W
SZ0
A4
8
1
Rev.6.00 Mar. 27, 2009 Page 297 of 1036
R/W
SZ1
A3
7
1
Section 12 Bus State Controller (BSC)
R/W
SZ0
A3
6
1
Description
Reserved (Setting disabled)
Byte (8-bit) size
Word (16-bit) size
Longword (32-bit) size
Reserved (Setting disabled)
Byte (8-bit) size
Word (16-bit) size
Reserved (Setting disabled)
R/W
SZ1
A2
5
1
R/W
SZ0
A2
4
1
—
R
3
0
REJ09B0254-0600
—
R
2
0
—
R
1
0
—
R
0
0