HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 912

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 27 I/O Ports
27.8
27.8.1
Note: * Undefined
Port L Data Register (PLDR) is an 8-bit read register that stores data for pins PTL7 to PTL2.
PL7DT to PL2DT bit corresponds to PTL7 to PTL2 pin. When the pin function is general input
port, if the port is read, the corresponding pin level is read. Table 27.7 shows the function of
PLDR.
PLDR is initialized to a power-on reset. It retains its previous value in software standby mode and
sleep mode, and by a manual reset.
Table 27.7 Read/Write Operation of the Port L Data Register (PLDR)
PLnMD1 PLnMD0 Pin State
0
1
Notes: *
Rev.6.00 Mar. 27, 2009 Page 854 of 1036
REJ09B0254-0600
Initial value:
1. Operation cannot be guaranteed when this bit it set to “reserved.”
Port L Data Register (PLDR)
Port L
0
1
*
Undefined
R/W:
Bit:
PL7DT
Other function H'00
Reserved *
Input
R
7
*
PL6DT
1
R
6
*
Read
⎯
Pin state
PL5DT
R
5
*
PL4DT
Write
Ignored (no affect on pin state)
⎯
Ignored (no affect on pin state)
R
4
*
PL3DT
R
3
*
PL2DT
R
2
*
—
R
1
*
(n = 2 to 7)
—
R
0
*