DF2166VTE33 Renesas Electronics America, DF2166VTE33 Datasheet - Page 242
![MCU FLASH 3V 512K 33MHZ 144TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2166VTE33
Manufacturer Part Number
DF2166VTE33
Description
MCU FLASH 3V 512K 33MHZ 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
- Current page: 242 of 876
- Download datasheet (5Mb)
8.5
Port 5 is an 8-bit I/O port. Port 5 pins also function as interrupt input pins, the PWMX output pin,
SCI_0, SCI_1, and SCI_2 input/output pins. Port 5 has the following registers.
• Port 5 data direction register (P5DDR)
• Port 5 data register (P5DR)
8.5.1
The individual bits of P5DDR specify input or output for the pins of port 5.
8.5.2
P5DR stores output data for the port 5 pins.
Rev. 3.00, 03/04, page 200 of 830
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name
P57DDR
P56DDR
P55DDR
P54DDR
P53DDR
P52DDR
P51DDR
P50DDR
Bit Name
P57DR
P56DR
P55DR
P54DR
P53DR
P52DR
P51DR
P50DR
Port 5
Port 5 Data Direction Register (P5DDR)
Port 5 Data Register (P5DR)
Initial Value
0
0
0
0
0
0
0
0
Initial Value
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
If port 5 pins are specified for use as the general I/O
port, the corresponding port 5 pins are output ports
when the P5DDR bits are set to 1, and input ports
when cleared to 0.
Description
P5DR stores output data for the port 5 pins that are
used as the general output port.
If a port 5 read is performed while the P5DDR bits are
set to 1, the P5DR values are read. If a port 5 read is
performed while the P5DDR bits are cleared to 0, the
pin states are read.
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