DF2166VTE33 Renesas Electronics America, DF2166VTE33 Datasheet - Page 591
![MCU FLASH 3V 512K 33MHZ 144TQFP](/photos/28/61/286114/144-tqfp_sml.jpg)
DF2166VTE33
Manufacturer Part Number
DF2166VTE33
Description
MCU FLASH 3V 512K 33MHZ 144TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.HS2168EPI61H-U.pdf
(876 pages)
Specifications of DF2166VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Bit
7 to 5
4
3
2
Bit Name Initial Value Slave Host Description
HDTWI
HDTRI
STARI
All 0
0
0
0
R/W
R/(W)*
R/(W)*
R/(W)*
R/W
Reserved
The initial value should not be changed.
Transfer Data Transmission End Interrupt
This is a status flag that indicates that the host has
finished transmitting the transfer data to SMICDTR.
When the IBFIE3 bit and HDTWIE bit are set to 1,
the IBFI3 interrupt is requested to the slave.
0: Transfer data transmission wait state
[Clearing condition]
After the slave reads HDTWI = 1, writes 0 to this bit.
1: Transfer data transmission end
[Setting condition]
The transfer cycle is write transfer and the host
writes the transfer data to SMICDTR.
Transfer Data Receive End Interrupt
This is a status flag that indicates that the host has
finished receiving the transfer data from SMICDTR.
When the IBFIE3 bit and HDTRIE bit are set to 1,
the IBFI3 interrupt is requested to the slave.
0: Transfer data receive wait state
[Clearing condition]
After the slave reads HDTRI = 1, writes 0 to this bit.
1: Transfer data receive end
[Setting condition]
The transfer cycle is read transfer and the host
reads the transfer data from SMICDTR.
Status Code Receive End Interrupt
This is a status flag that indicates that the host has
finished receiving the status code from SMICCSR.
When the IBFIE3 bit and STARIE bit are set to 1, the
IBFI3 interrupt is requested to the slave.
0: Status code receive wait state
[Clearing condition]
After the slave reads STARI = 1, writes 0 to this bit.
1: Status code receive end
[Setting condition]
When the host reads the status code of SMICCSR.
Rev. 3.00, 03/04, page 549 of 830
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