M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 407
![IC M16C MCU FLASH 100QFP](/photos/12/43/124347/m30624fgafp_u3_sml.jpg)
M30624FGAFP#U3
Manufacturer Part Number
M30624FGAFP#U3
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.M30622SAFPU5.pdf
(277 pages)
2.M30622SAFPU5.pdf
(617 pages)
3.M30622SAFPU5.pdf
(308 pages)
Specifications of M30624FGAFP#U3
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30624FGAFP#U3M30624FGAFP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30624FGAFP#U3M30624FGAFP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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UART
2-88
Operation
2.5.3 Operation of Serial I/O (reception in UART mode)
In receiving data in UART mode, choose functions from those listed in Table 2.5.5. Operations of the
circled items are described below. Figure 2.5.11 shows the operation timing, and Figures 2.5.12 and
2.5.13 show the set-up procedures.
Table 2.5.5. Choosed functions
Note 1: UART0, UART1 only.
Note 2: UART2 only.
(1) Setting the receive enable bit to “1” readies data-receivable status. At this time, output from
(2) When the first bit (the start bit) of reception data is received from the RxDi pin, output from the
(3) When the stop bit(s) is (are) received, the content of the UARTi receive register is transmitted
At this time, the receive complete flag goes to “1” to indicate that the reception is completed, the
(4) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register
Transfer clock
source
(Note 1)
RTS function
Sleep mode
(Note 1)
the RTSi pin goes to “L” level to inform the transmission side that the receivable status is
ready.
_______
RTS goes to “H” level. Then, data is received, bit by bit, in sequence: LSB, ····, MSB, and stop
bit(s).
to the UARTi receive buffer register.
UARTi receive interrupt request bit goes to “1”, and output from the RTS pin goes to “H” level.
is read.
________
Item
O
O
O
Internal clock (f
External clock (CLKi pin)
RTS function enabled
Sleep mode off
RTS function disabled
Sleep mode selected
Set-up
1
/ f
8
/ f
32
)
Data logic select
function
(Note 2)
T
polarity reverse bit
(Note 2)
Bus collision
detection function
(Note 2)
X
D, R
X
Item
D I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
O
O
O
_______
Not selected
No reverse
Reverse
No reverse
Reverse
Selected
M16C / 62A Group
Mitsubishi microcomputers
Set-up
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