M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 560

• Manufacturer Part Number: M30624FGAFP#U3
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGAFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

External Buses
4.5 Releasing an External Bus (HOLD input and HLDA output)
The Hold feature is to relinquish the address bus, the data bus, and the control bus on M16C/62A side in
line with the Hold request from the bus master other than M16C/62A when the two or more bus masters
share the address bus, the data bus, and the control bus. The Hold feature is effective only in memory
expansion mode and microprocessor mode.
The sequence of using the Hold feature may be:
As given above, each bus invariably gets in the high-impedance state while the HLDA output is “L”. Also,
M16C/62A does not relinquish buses during a bus cycle. That is, if a Hold request comes in during a bus
cycle, the HLDA output become “L” after that bus cycle finishes.
In the Hold state, the state of each terminal becomes as follows.
Figure. 4.5.1 shows an example of relinquishing external buses.
1. The external bus master turns the input level of the HOLD terminal to “L”.
2. When M16C/62A becomes ready to relinquish buses, each bus becomes high-impedance state at the
3. The HLDA terminal becomes “L” at the rising edge of the next BCLK.
4. The external bus master uses a bus.
5. When the external bus master finishes using a bus, the external bus master returns the input level of
6. The output from HLDA terminal becomes “H” at the rising edge of the next BCLK.
7. Each bus returns from the high-impedance state to the former state at the falling edge of the next
• Address bus A
• Data bus D
• RD, WR, WRL, WRH, BHE
• ALE
• CS0 to CS3
_____
_______
High-impedance state. The case in which A
space) and the case in which A
whole area) in microprocessor mode and in memory expansion mode too fall under this category.
High-impedance state. The case in which D
width) and the case in which D
whole area) in microprocessor mode and in memory expansion mode too fall under this category.
High-impedance state.
An internal clock signal having the same phase as BCLK is output.
High-impedance state. The case in which ports are selected by the chip selection control register too
falls under this category.
falling edge of BCLK.
the HOLD terminal to “H”.
BCLK.
______
__________
__________
__________
_______
________ _________ ________
0
to D
0
__________
15
to A
19
0
9
__________
to D
to A
15
19
are used as ports P0
are used as ports P3
16
8
to D
to A
19
15
__________
are used as ports P4
are used as ports P1
_________
0
1
to P0
to P3
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
7
and P1
and P4
0
0
__________
to P4
to P1
0
0
to P1
to P4
3
7
M16C / 62A Group
(64K byte address
Mitsubishi microcomputers
7
3
(8-bit external bus
(multiplex for the
(multiplex for the
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