M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 497

• Manufacturer Part Number: M30624FGAFP#U3
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGAFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2-178
Power Control
Operation
Figure 2.15.5. Example of stop mode set-up
2.15.2 Stop Mode Set-Up
Settings and operation for entering stop mode are described here.
(3) All clocks off (stop mode)
Insert at least four NOPs after the instruction that sets the all clock stop control bit to “1”.
(3) Setting operation clock after returning from stop mode
b7
(3) Canceling protect
(1) Setting interrupt to cancel stop mode
b7
b7
b7
(2) Interrupt enable flag (I flag)
0
As this register becomes setting mentioned above when
operating with X
the user does not need to set it again.
(When operating with X
(1) Enables the interrupt used for returning from stop mode.
(2) Sets the interrupt enable flag (I flag) to “1”.
(3) Clearing the protection and setting all clock stop control bit to “1” stops oscillation and causes
0
0
the processor to go into stop mode.
0
Interrupt control register
TBiIC(i=3 to 5)
BCNIC
KUPIC
SiTIC(i=0 to 2)
SiRIC(i=0 to 2)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
0
IN
(count source of BCLK is X
0
b0
b0
b0
1
b0
1
Interrupt priority level select bit
Make sure that the interrupt priority
level of the interrupt which is used to
cancel the wait mode is higher than
the processor interrupt priority(IPL) of
the routine where the WAIT
instruction is executed.
Main clock (X
All clock stop control bit
Reserved bit
Enables writing to system clock control registers 0 and 1
(addresses 0006
System clock select bit
Protect register [Address 000A
PRCR
System clock control register
[Address 0006
System clock control register [Address 0007
CM1
1 : All clocks off (stop mode)
Must always be set to “0”
1 : Write-enabled
X
On
IN
IN
, X
[Address 0045
[Address 004A
[Address 004D
[Address 0051
[Address 0052
[Address 0055
[Address 005A
after returning)
OUT
IN
16
-X
] CM0
16
OUT
“1”
16
16
16
16
and 0007
IN
16
16
16
, 0053
, 0054
) stop bit
),
]
]
to 0047
to 0059
to 005C
16
16
All clocks off (stop mode)
16
, 004F
, 0050
16
16
16
)
]
]
16
]
]
16
16
b7
]
]
b7
1
As this register becomes setting mentioned above when operating with X
(count source of BCLK is X
When operating with X
select bit to “1”. The both bits cannot be set at the same time.
(When operating with X
0
INTiIC(i=3)
SiIC/INTjIC(i=4, 3)
INTiIC(i=0 to 2)
16
]
1
(j=3, 4)
b0
b0
IN
Interrupt priority level select bit
Reserved bit
, set port Xc select bit to “1” before setting system clock
Must always be set to “0”
[Address 0044
[Address 0048
[Address 0048
[Address 005D
Make sure that the interrupt priority level of the
interrupt which is used to cancel the wait mode is
higher than the processor interrupt priority(IPL) of
the routine where the WAIT instruction is executed.
Port X
System clock control register 0
[Address 0006
System clock select bit
CIN
X
X
CIN
CIN
CIN
), the user does not need to set it again.
C
, X
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
-X
after returning)
select bit
COUT
COUT
16
16
16
generation
16
16
]
, 0049
, 0049
] CM0
to 005F
16
16
]
]
16
]
M16C / 62A Group
Mitsubishi microcomputers
CIN