UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 260

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(6) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D) (products other than
(7) CPU clock changing from internal high-speed oscillation clock (B) to 40 MHz internal high-speed
258
(8) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
Status Transition
(B) → (D)
Status Transition
(B) → (J)
Status Transition
(C) → (B)
Note The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release.
Remark (A) to (K) in Table 5-5 correspond to (A) to (K) in Figure 5-15 and Figure 5-16.
78K0R/IB3)
oscillation clock (J)
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (3/6)
Setting Flag of SFR Register
Setting Flag of SFR Register
CHAPTER 5 CLOCK GENERATOR
User’s Manual U19678EJ1V1UD
CMC Register
CPU is operating with
Unnecessary if the CPU is operating
with the 40 MHz internal high-speed
Unnecessary if the
the internal high-
speed oscillation
OSCSELS
DSCCTL
Register
CSC Register
DSCON
HIOSTOP
1
1
clock
Unnecessary if the CPU is operating
0
oscillation clock
Note
with the subsystem clock
CSC Register
Stabilization
Waiting for
Necessary
Oscillation
XTSTOP
(100
0
Oscillation accuracy
μ
stabilization time
s)
10
μ
s
Stabilization
Waiting for
Necessary
Oscillation
DSCCTL
Register
DSPO
1
CKC Register
MCM0
CKC Register
DSCCTL
SELDSC
0
Register
CSS
1
1