UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 263

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(13) • HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
(14) • STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
(B) → (E)
(C) → (F)
(D) → (G)
(J) → (K)
(B) → (H)
(C) → (I)
Remark (A) to (K) in Table 5-5 correspond to (A) to (K) in Figure 5-15 and Figure 5-16.
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D) (products other than 78K0R/IB3)
• HALT mode (K) set while CPU is operating with 40 MHz internal high-speed oscillation clock (J)
• STOP mode (I) set while CPU is operating with high-speed system clock (C)
Status Transition
Status Transition
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (6/6)
(Setting sequence)
In X1
oscillation
External main
system clock
CHAPTER 5 CLOCK GENERATOR
User’s Manual U19678EJ1V1UD
Executing HALT instruction
Stopping peripheral
functions that cannot
operate in STOP mode
Sets the OSTS
register
Setting
Setting
−
−
Executing STOP
instruction
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