UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 883

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
PR11H, PR12L, PR12H)
The priority specification flag registers are used to set the corresponding maskable interrupt priority level.
A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L, or 2H).
PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, and PR12H can be
set by a 1-bit or 8-bit memory manipulation instruction. If PR00L and PR00H, PR01L and PR01H, PR02L and
PR02H, PR10L and PR10H, PR11L and PR11H, and PR12L and PR12H are combined to form 16-bit registers
PR00, PR01, PR02, PR10, PR11, and PR12, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
(Note is listed on the next page after next.)
Address: FFFE8H
Address: FFFECH
Address: FFFE9H
Address: FFFEDH
(PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (1/3)
Symbol
Symbol
Symbol
Symbol
PR00H
PR10H
PR00L
PR10L
increases by 2 clocks.
SREPR00
SREPR10
PPR05
PPR15
<7>
<7>
<7>
<7>
After reset: FFH
After reset: FFH
After reset: FFH
After reset: FFH
Figure 17-4. Format of Priority Specification Flag Registers
CSIPR001
CSIPR101
SRPR00
SRPR10
PPR04
PPR14
<6>
<6>
<6>
<6>
Note 1
Note 1
CHAPTER 17 INTERRUPT FUNCTIONS
CSIPR000
CSIPR100
R/W
TMOFFPR00
TMOFFPR10
R/W
R/W
R/W
PPR03
PPR13
STPR00
STPR10
<5>
<5>
<5>
<5>
User’s Manual U19678EJ1V1UD
Note 1
Note 1
DMAPR01
DMAPR11
PPR02
PPR12
<4>
<4>
<4>
<4>
DMAPR00
DMAPR10
PPR01
PPR11
<3>
<3>
<3>
<3>
CMPPR01
CMPPR11
PPR00
PPR10
<2>
<2>
<2>
<2>
CMPPR00
CMPPR10
LVIPR0
LVIPR1
<1>
<1>
<1>
<1>
TMADPR0
TMADPR1
WDTIPR0
WDTIPR1
<0>
<0>
<0>
<0>
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