UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 733

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.6.6 Procedure for processing errors that occurred during UART (UART0, UART1) communication
Figures 13-91 and 13-92.
Reads serial data register 0n
(SDR0n).
Reads serial status register 0n (SSR0n).
Writes 1 to serial flag clear trigger
register 0n (SIR0n).
Reads serial data register 0n
(SDR0n).
Reads serial status register 0n (SSR0n).
Writes serial flag clear trigger register 0n
(SIR0n).
Sets ST0n bit of serial channel stop
register 0 (ST0) to 1.
Synchronization with other party of
communication
Sets SS0n bit of the serial channel start
register 0 (SS0) to 1.
The procedure for processing errors that occurred during UART (UART0, UART1) communication is described in
Remark n: Channel number (n = 0 to 3)
Software Manipulation
Software Manipulation
Figure 13-91. Processing Procedure in Case of Parity Error or Overrun Error
Figure 13-92. Processing Procedure in Case of Framing Error
CHAPTER 13 SERIAL ARRAY UNIT
The BFF0n bit of the SSR0n register is
set to 0 and channel n is enabled to
receive data.
Error flag is cleared.
The BFF0n bit of the SSR0n register is
set to 0 and channel n is enabled to
receive data.
Error flag is cleared.
The SE0n bit of the serial channel
enable status register 0 (SE0) is set to
0 and channel n stops operating.
The SE0n bit of the serial channel
enable status register 0 (SE0) is set to
1 and channel n is enabled to operate.
User’s Manual U19678EJ1V1UD
Hardware Status
Hardware Status
This is to prevent an overrun error if the
next reception is completed during error
processing.
Error type is identified and the read
value is used to clear error flag.
Error can be cleared only during
reading, by writing the value read from
the SSR0n register to the SIR0n register
without modification.
This is to prevent an overrun error if the
next reception is completed during error
processing.
Error type is identified and the read
value is used to clear error flag.
Error can be cleared only during
reading, by writing the value read from
the SSR0n register to the SIR0n register
without modification.
Synchronization with the other party of
communication is re-established and
communication is resumed because it is
considered that a framing error has
occurred because the start bit has been
shifted.
Remark
Remark
731