UPD78F1211GB-GAF-AX Renesas Electronics America, UPD78F1211GB-GAF-AX Datasheet - Page 639

• Manufacturer Part Number: UPD78F1211GB-GAF-AX
• Description: MCU 16BIT 78K0R/LX3 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.4.1 Stopping the operation by units
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
The stopping of the operation by units is set by using peripheral enable register 0 (PER0).
PER0 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
To stop the operation of serial array unit, set bit 2 (SAU0EN) to 0.
PER0
Figure 13-22. Peripheral Enable Register 0 (PER0) Setting When Stopping the Operation by Units
Cautions 1. If SAU0EN = 0, writing to a control register of serial array unit is ignored, and, even if the
Remark
Notes
(a) Peripheral enable register 0 (PER0)
RTCEN
1.
2.
×
7
2. Be sure to clear bits 0, 1, 3, and 6(78K0R/IB3: Bits 0, 1, 3, 4, 6, and 7 and 38-pin and 44-pin
×: Bits not used with serial array units (depending on the settings of other peripheral functions)
0/1: Set to 0 or 1 depending on the usage of the user
Note 1
: Setting disabled (fixed by hardware)
RTCEN bit is not provided in the 78K0R/IB3. In the 78K0R/IB3, bit7 of PER0 register is fixed to 0.
IICAEN bit is not provided in the 78K0R/IB3 and the 38-pin and 44-pin of the 78K0R/IC3. In the
78K0R/IB3 and the 38-pin and 44-pin of the 78K0R/IC3, bit4 of PER0 register is fixed to 0.
register is read, only the default value is read (except for input switch control register
(ISC), noise filter enable register (NFEN0), port input mode registers (PIM3, PIM7), port
output mode registers (POM3, POM7), port mode registers (PM3, PM7), and port registers
(P3, P7)).
products of 78K0R/IC3: Bits 0, 1, 3, 4, and 6 ) of PER0 register to 0.
6
0
ADCEN
CHAPTER 13 SERIAL ARRAY UNIT
×
5
1: Enables input clock supply
User’s Manual U19678EJ1V1UD
0: Stops input clock supply
Control of SAU input clock
IICAEN
4
×
Note 2
3
0
SAU0EN
0/1
2
1
0
0
0
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