UPD70F3745GJ-GAE-AX Renesas Electronics America, UPD70F3745GJ-GAE-AX Datasheet - Page 514

no-image

UPD70F3745GJ-GAE-AX

Manufacturer Part Number
UPD70F3745GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet

Specifications of UPD70F3745GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
128
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
60K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3745GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3745GJ-GAE-AX/JS
Manufacturer:
EPSON
Quantity:
188
Part Number:
UPD70F3745GJ-GAE-AX/JS
Manufacturer:
RENESAS
Quantity:
1 000
V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
Therefore, the maximum baud rate that can be received by the destination is as follows.
Similarly, obtaining the following maximum allowable transfer rate yields the following.
Therefore, the minimum baud rate that can be received by the destination is as follows.
Obtaining the allowable baud rate error for UARTAn and the destination from the above-described equations for
obtaining the minimum and maximum baud rate values yields the following.
Remarks 1. The reception accuracy depends on the bit count in 1 frame, the input clock
10
11
4
8
20
50
100
255
Division Ratio (k)
BRmax = (FLmin/11)
BRmin = (FLmax/11)
× FLmax = 11 × FL −
FLmax =
2. k: Setting value of UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (n = 0 to 3)
frequency, and the division ratio (k). The higher the input clock frequency and
the larger the division ratio (k), the higher the accuracy.
Table 15-4. Maximum/Minimum Allowable Baud Rate Error
21k − 2
20 k
Maximum Allowable Baud Rate Error
1
1
=
FL × 11
=
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
k + 2
2 × k
21k − 2
21k + 2
20k
22k
+2.32%
+3.52%
+4.26%
+4.56%
+4.66%
+4.72%
× FL =
Brate
Brate
21k − 2
2 × k
FL
Minimum Allowable Baud Rate Error
−2.43%
−3.61%
−4.30%
−4.58%
−4.67%
−4.72%
Page 498 of 892

Related parts for UPD70F3745GJ-GAE-AX