UPD70F3745GJ-GAE-AX Renesas Electronics America, UPD70F3745GJ-GAE-AX Datasheet - Page 696

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UPD70F3745GJ-GAE-AX

Manufacturer Part Number
UPD70F3745GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet

Specifications of UPD70F3745GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
128
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
60K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3745GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3745GJ-GAE-AX/JS
Manufacturer:
EPSON
Quantity:
188
Part Number:
UPD70F3745GJ-GAE-AX/JS
Manufacturer:
RENESAS
Quantity:
1 000
V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
(2) Restoration
Restoration from a debug trap is executed with the DBRET instruction.
With the DBRET instruction, the CPU performs the following steps and transfers control to the address of the
restored PC.
<1> The restored PC and PSW are read from DBPC and DBPSW.
<2> Control is transferred to the fetched address of the restored PC and PSW.
Caution DBPC and DBPSW can be accessed only during the interval between the execution of the
The processing format for restoration from a debug trap is shown below.
DBTRAP instruction and the DBRET instruction.
Figure 19-14. Processing Format of Restoration from Debug Trap
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Jump to address of restored PC
PC
PSW
DBRET instruction
DBPC
DBPSW
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