UPD70F3745GJ-GAE-AX Renesas Electronics America, UPD70F3745GJ-GAE-AX Datasheet - Page 624

• Manufacturer Part Number: UPD70F3745GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3745GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 60K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
17.14 Communication Reservation
17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0)
enable transmission of a start condition when the bus is released. There are two modes in which the bus is not used.
set after the bus is released (after a stop condition is detected).
address transfer to start. At this point, the IICCn.SPIEn bit should be set to 1 (n = 0 to 2).
according to the bus status (n = 0 to 2).
then check the IICSn.MSTSn bit (n = 0 to 2).
CLn1, and CLn0 bits of the IICCLn register and the IICXn.CLXn bit (n = 0 to 2).
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
To start master device communications when not currently using the bus, a communication reservation can be made to
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released
If the IICCn.STTn bit is set to 1 while the bus is not used, a start condition is automatically generated and a wait state is
When the bus release is detected (when a stop condition is detected), writing to the IICn register causes master
When STTn has been set to 1, the operation mode (as start condition or as communication reservation) is determined
If the bus has been released .............................................A start condition is generated
If the bus has not been released (standby mode)..............Communication reservation
To detect which operation mode has been determined for the STTn bit, set the STTn bit to 1, wait for the wait period,
The wait periods, which should be set via software, are listed in Table 17-6. These wait periods can be set by the SMCn,
when the IICCn.LRELn bit was set to 1) (n = 0 to 2).
CHAPTER 17 I
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C BUS