UPD70F3745GJ-GAE-AX Renesas Electronics America, UPD70F3745GJ-GAE-AX Datasheet - Page 538

• Manufacturer Part Number: UPD70F3745GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3745GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 60K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
SIBn pin capture
INTCBnR signal
(2) Operation timing
CBnTSF bit
SCKBn pin
SIBn pin
(1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A1H to the CBnCTL0 register, and select the reception mode and MSB first at the same time as
(4) The CBnSTR.CBnTSF bit is set to 1 by performing a dummy read of the CBnRX register, and the
(5) When a serial clock is input, capture the receive data of the SIBn pin in synchronization with the serial
(6) When reception of the transfer data length set with the CBnCTL2 register is completed, stop the serial
(7) To continue reception, read the CBnRX register with the CBnCTL0.CBnSCE bit = 1 remained after the
(8) To end reception, write the CBnSCE bit = 0.
(9) Read the CBnRX register.
(10) To end reception, write the CBnCTL0.CBnPWR bit = 0 and the CBnCTL0.CBnRXE bit = 0.
Remark
timing
external clock (SCKBn), and slave mode.
enabling the operation of the communication clock (f
device waits for a serial clock input.
clock.
clock input and data capturing, generate the reception completion interrupt request signal (INTCBnR)
at the last edge of the serial clock, and clear the CBnTSF bit to 0.
INTCBnR signal is generated, and wait for a serial clock input.
(1)
(2)
(3)
n = 0 to 5
(4)
(5)
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
Bit 1
(6)
Bit 0
(7)
CCLK
Bit 7
).
Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
(8)
(9)
(10)
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CCLK
) =