PIC16LC774/PQ Microchip Technology, PIC16LC774/PQ Datasheet - Page 137

• Manufacturer Part Number: PIC16LC774/PQ
• Description: IC MCU OTP 4KX14 A/D PWM 44-MQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC774/PQ

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-MQFP, 44-PQFP
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, SSP, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.10
The PIC16C77X family has up to 14 sources of inter-
rupt. The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has indi-
vidual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 12-11: INTERRUPT LOGIC
The following table shows which devices have which interrupts.
PIC16C773
PIC16C774
Note:
1999 Microchip Technology Inc.
Device
LVDIF
LVDIE
PSPIF
PSPIE
CCP2IF
CCP2IE
BCLIF
BCLIE
Interrupts
Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
ADIF
ADIE
TMR1IF
TMR1IE
T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
Yes
Yes
RCIF
RCIE
TMR2IF
TMR2IE
Yes
Yes
Yes
Yes
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
Yes
-
Yes
Yes
Advance Information
Yes
Yes
Yes
Yes
Yes
Yes
T0IF
T0IE
INTF
INTE
RBIF
RBIE
PEIE
GIE
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set regardless of the status of
their corresponding mask bit or the GIE bit
Yes
Yes
Yes
Yes
Yes
Yes
PIC16C77X
Wake-up (If in SLEEP mode)
LVDIF
Yes
Yes
DS30275A-page 137
Interrupt to CPU
BCLIF
Yes
Yes
CCP2IF
Yes
Yes