PIC16LC774/PQ Microchip Technology, PIC16LC774/PQ Datasheet - Page 73

• Manufacturer Part Number: PIC16LC774/PQ
• Description: IC MCU OTP 4KX14 A/D PWM 44-MQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC774/PQ

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-MQFP, 44-PQFP
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, SSP, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

i)
j)
k)
l)
8.2.8
In I
located in the lower 7 bits of the SSPADD register
(Figure
the BRG counts down to 0 and stops until another
reload has taken place. The BRG count is decremented
twice per instruction cycle (T
clock.
FIGURE 8-19: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
1999 Microchip Technology Inc.
2
C master mode, the reload value for the BRG is
The MSSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The user generates a STOP condition by setting
the STOP enable bit PEN in SSPCON2.
Interrupt is generated once the STOP condition
is complete.
8-18). When the BRG is loaded with this value,
BAUD RATE GENERATOR
SDA
SCL
BRG
value
BRG
reload
03h
CY
) on the Q2 and Q4
DX
SCL de-asserted but slave holds
SCL low (clock arbitration)
02h
SCL is sampled high, reload takes
place, and BRG starts its count.
Advance Information
01h
BRG decrements
(on Q2 and Q4 cycles)
00h (hold off)
DX-1
In I
If Clock Arbitration is taking place for instance, the BRG
will be reloaded when the SCL pin is sampled high
(Figure
FIGURE 8-18: BAUD RATE GENERATOR
SSPM3:SSPM0
2
SSPM3:SSPM0
C master mode, the BRG is reloaded automatically.
8-19).
SCL
SCL allowed to transition high
CLKOUT
03h
BLOCK DIAGRAM
Reload
Control
PIC16C77X
02h
BRG Down Counter
SSPADD<6:0>
Reload
DS30275A-page 73
Fosc/4