ATMEGA64-16AJ Atmel, ATMEGA64-16AJ Datasheet - Page 171
![IC MCU AVR 64K 5V 16MHZ 64-TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA64-16AJ
Manufacturer Part Number
ATMEGA64-16AJ
Description
IC MCU AVR 64K 5V 16MHZ 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64-16AJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part Number
Manufacturer
Quantity
Price
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USART
Dual USART
Overview
2490Q–AVR–06/10
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device. The main features are:
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The ATmega64 has two USART’s, USART0 and USART1. The functionality for both USART’s is
described below. USART0 and USART1 have different I/O Registers as shown in
Summary” on page
neither is the UBRR0H or UCRS0C registers. This means that in ATmega103 compatibility
mode, the ATmega64 supports asynchronous operation of USART0 only.
A simplified block diagram of the USART Transmitter is shown in
Registers and I/O pins are shown in bold.
Figure 79. USART Block Diagram
Note:
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
1. Refer to
placement.
Figure 1 on page
370. Note that in ATmega103 compatibility mode, USART1 is not available,
UCSRA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
(1)
2,
UDR (Transmit)
UDR (Receive)
UBRR[H:L]
Table 36 on page
UCSRB
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
CHECKER
PARITY
CLOCK
PARITY
DATA
OSC
78, and
Table 39 on page 81
Clock Generator
Figure
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
TX
RX
Receiver
UCSRC
ATmega64(L)
79. CPU accessible I/O
XCK
RxD
TxD
for USART pin
“Register
171
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