ATMEGA64-16AJ Atmel, ATMEGA64-16AJ Datasheet - Page 269
![IC MCU AVR 64K 5V 16MHZ 64-TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA64-16AJ
Manufacturer Part Number
ATMEGA64-16AJ
Description
IC MCU AVR 64K 5V 16MHZ 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64-16AJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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Table 105. Algorithm for Using the ADC
Note:
2490Q–AVR–06/10
Ste
p
1
2
3
4
5
6
7
8
9
10
11
Actions
SAMPLE_PRELOAD
EXTEST
Verify the COMP bit scanned out to be 0
Verify the COMP bit scanned out to be 1
1. Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock frequency. As the algorithm keeps
HOLD high for five steps, the TCK clock frequency has to be at least five times the number of scan bits divided by the maxi-
mum hold time, t
hold,max
The recommended values from
rithm in
“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register
with the succeeding columns. The verification should be done on the data scanned out when
scanning in the data on the same row in the table.
.
Table
(1)
105. Only the DAC and Port Pin values of the Scan-chain are shown. The column
ADCEN
1
1
1
1
1
1
1
1
1
1
1
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
DAC
Table 104
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
are used unless other values are given in the algo-
HOLD
1
0
1
1
1
1
0
1
1
1
1
PRECH
1
1
1
1
0
1
1
1
1
0
1
PA3.
Data
ATmega64(L)
0
0
0
0
0
0
0
0
0
0
0
Control
PA3.
0
0
0
0
0
0
0
0
0
0
0
Enable
Pull-
PA3.
up_
0
0
0
0
0
0
0
0
0
0
0
269
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