AT90CAN128-16MI Atmel, AT90CAN128-16MI Datasheet - Page 222
![IC MCU AVR FLASH 128K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MI
Manufacturer Part Number
AT90CAN128-16MI
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Price
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Part Number:
AT90CAN128-16MI
Manufacturer:
ATMEL
Quantity:
430
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AT90CAN128-16MI
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18.8.2
222
AT90CAN32/64/128
Master Receiver Mode
In the Master Receiver Mode, a number of data bytes are received from a slave transmitter (see
Figure
mat of the following address packet determines whether Master Transmitter or Master Receiver
mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted,
MR mode is entered. All the status codes mentioned in this section assume that the prescaler
bits are zero or are masked to zero.
Figure 18-13. Data Transfer in Master Receiver Mode
A START condition is sent by writing the following value to TWCR:
TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written to
one to transmit a START condition and TWINT must be set to clear the TWINT flag. The TWI will
then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes
free. After a START condition has been transmitted, the TWINT flag is set by hardware, and the
status code in TWSR will be 0x08 (See
transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit should be
cleared (by writing it to one) to continue the transfer. This is accomplished by writing the follow-
ing value to TWCR:
When SLA+R have been transmitted and an acknowledgment bit has been received, TWINT is
set again and a number of status codes in TWSR are possible. Possible status codes in Master
mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes
is detailed in
flag is set high by hardware. This scheme is repeated until the last byte has been received. After
the last byte has been received, the MR should inform the ST by sending a NACK after the last
received data byte. The transfer is ended by generating a STOP condition or a repeated START
condition. A STOP condition is generated by writing the following value to TWCR:
TWCR
value
TWCR
value
TWCR
value
18-13). In order to enter a Master mode, a START condition must be transmitted. The for-
SDA
SCL
TWINT
TWINT
TWINT
Table
1
1
1
18-12. Received data can be read from the TWDR Register when the TWINT
Device 1
RECEIVER
MASTER
TWEA
TWEA
TWEA
X
X
X
TWSTA
TWSTA
TWSTA
1
0
0
TRANSMITTER
Device 2
SLAVE
Table
TWSTO
TWSTO
TWSTO
0
0
1
18-3). In order to enter MR mode, SLA+R must be
Device 3
TWWC
TWWC
TWWC
X
X
X
........
TWEN
TWEN
TWEN
1
1
1
Device n
–
0
–
0
–
0
R1
TWIE
TWIE
TWIE
7679H–CAN–08/08
X
X
X
V
CC
R2
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