AT90CAN128-16MI Atmel, AT90CAN128-16MI Datasheet - Page 278
![IC MCU AVR FLASH 128K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MI
Manufacturer Part Number
AT90CAN128-16MI
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90CAN128-16MI
Manufacturer:
ATMEL
Quantity:
430
Company:
Part Number:
AT90CAN128-16MI
Manufacturer:
ATMEL
Quantity:
246
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21.4.1
278
AT90CAN32/64/128
Differential Channels
Figure 21-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 21-7. ADC Timing Diagram, Free Running Conversion
Table 21-1.
When using differential channels, certain aspects of the conversion need to be taken into
consideration.
Differential conversions are synchronized to the internal clock CK
clock frequency. This synchronization is done automatically by the ADC interface in such a way
that the sample-and-hold occurs at a specific phase of CK
user (i.e., all single conversions, and the first free running conversion) when CK
take the same amount of time as a single ended conversion (13 ADC clock cycles from the next
prescaled clock cycle). A conversion initiated by the user when CK
clock cycles due to the synchronization mechanism. In Free Running mode, a new conversion is
Condition
Sample & Hold (Cycles from Start of
Convention)
Conversion Time (Cycles)
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Conversion
ADC Conversion Time
Complete
Prescaler
Reset
One Conversion
11
12
MUX and REFS
Update
1
13
2
Next Conversion
1
Sign and MSB of Result
LSB of Result
3
2
MUX and REFS
Update
Sample &
Hold
4
3
5
Sample & Hold
4
6
7
One Conversion
8
Conversion
9
First
14.5
25
10
Conversion
Complete
11
12
ADC2
13
Single Ended
. A conversion initiated by the
Conversion,
ADC2
Sign and MSB of Result
Normal
ADC2
LSB of Result
1.5
13
Next Conversion
is high will take 14 ADC
equal to half the ADC
1
Prescaler
Reset
2
ADC2
7679H–CAN–08/08
Conversion
Triggered
Auto
13.5
is low will
2
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