ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 12
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ATMEGA8HVD-4MX
Manufacturer Part Number
ATMEGA8HVD-4MX
Description
MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8HVD-4MX.pdf
(168 pages)
Specifications of ATMEGA8HVD-4MX
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.4 V
Data Converters
A/D 1x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
18-MLF® Exposed Pad (Staggered Leads), DFN
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
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ATmega4HVD/8HVD
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All
enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set
when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt
Vector in order to execute the interrupt handling routine, and hardware clears the correspond-
ing interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit
position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt
enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is
enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur
while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set
and remembered until the Global Interrupt Enable bit is set, and will then be executed by order
of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before
the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute
one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine,
nor restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately dis-
abled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously
with the CLI instruction. The following example shows how this can be used to avoid interrupts
during the timed EEPROM write sequence.
Assembly Code Example
C Code Example
in r16, SREG
cli
sbi EECR, EEMWE
sbi EECR, EEWE
out SREG, r16
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG; /* restore SREG value (I-bit) */
; disable interrupts during timed sequence
; store SREG value
; start EEPROM write
; restore SREG value (I-bit)
8052B–AVR–09/08
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