ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 78

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

16.5.4
16.5.5
16.5.6
16.6
78
Input Capture Unit
ATmega4HVD/8HVD
Clear Timer on Compare Match (CTC) 16-bit Mode
8-bit Input Capture Mode
16-bit Input Capture Mode
are no special cases to consider in the Normal mode, a new counter value can be written any-
time. The Output Compare Unit can be used to generate interrupts at some given time.
In Clear Timer on Compare 16-bit mode, OCRAnA/B Registers are used to manipulate the
counter resolution, see
cleared to zero when the counter value (TCNTn) matches OCRnA/B, where OCRnB repre-
sents the eight most significant bits and OCRnA represents the eight least significant bits.
OCRnA/B defines the top value of the counter, hence also its resolution. This mode allows
greater control of the Compare Match output frequency. It also simplifies the operation of
counting external events.
An interrupt can be generated each time the counter reaches the TOP value by using the
OCFnA flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing the TOP to a value close the BOTTOM when the counter
is running with none or a low prescaler value must be done with care since the CTC mode
does not have the double buffering feature. If the new value written to OCRnA/B is lower than
the current value of TCNTn, the counter will miss the Compare Match. The counter will then
have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before
Compare Match can occur. As for the 16-bit Mode, the TOVn Flag is set in the same timer
clock cycle that the counter counts from MAX to 0x0000.
The Timer/Counter can be used in a 8-bit Input Capture mode, see
bit settings. For full description, see
The Timer/Counter can also be used in a 16-bit Input Capture mode, see
76
The Timer/Counter incorporates an Input Capture unit that can capture external events and
give them a time-stamp indicating time of occurrence. The external signal indicates an event,
or multiple events. For Timer/Counter0, the events can be applied via the PC0 pin (ICP00), or
alternatively via the osi_posedge pin on the Oscillator Sampling Interface (ICP01). For
Timer/Counter1, the events can be applied by the Battery Protection Interrupt (ICP10) or alter-
natively by the Voltage Regulator Interrupt (ICP11). The time-stamps can then be used to
calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-
stamps can be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram shown in
The elements of the block diagram that are not directly a part of the Input Capture unit are gray
shaded.
for bit settings. For full description, see
Table 16-2 on page 76
”Input Capture Unit” on page
”Input Capture Unit” on page
for bit settings. In CTC mode the counter is
78.
Table 16-2 on page 76
Figure 16-4 on page
78.
Table 16-2 on page
8052B–AVR–09/08
79.
for