ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 91

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

17.2
17.3
17.4
8052B–AVR–09/08
Operation
Starting a Conversion
Conversion Timing
The ADC converts an analog input voltage to a 10-bit digital value through successive approx-
imation. For the PV1 pin the minimum value represents GND and the maximum value
represents 5 times the internal 1.1V reference voltage. For the ADC0 pin the minimum value
represents AGND and the maximum value represents the internal 1.1V reference voltage.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. The ADC does not
consume power when ADEN is cleared, so it is recommended to switch off the ADC before
entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. The result is presented right adjusted.
ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs
to the same conversion. Once ADCL is read, ADC access to data registers is blocked. This
means that if ADCL has been read, and a conversion completes before ADCH is read, neither
register is updated and the result from the conversion is lost. When ADCH is read, ADC
access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When
ADC access to the data registers is prohibited between reading of ADCH and ADCL, the inter-
rupt will trigger even if the result is lost.
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be cleared by hardware
when the conversion is completed.
When initiating a conversion by setting the ADSC bit in ADCSRA, the conversion starts at the
following rising edge of the ADC clock cycle. If the system clock prescaler setting is changed
during a ADC conversion, the conversion result may be invalid and should be discarded.
When PV1 or ADC0 is selected, a conversion takes 13 ADC clock cycles. When the internal
temperature sensor is selected, the conversion takes 27 ADC cycles. The first conversion
after the ADC is switched on (ADEN in ADCSRA is set) takes 27 ADC clock cycles in order to
initialize the analog circuitry.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal con-
version and 16.5 ADC clock cycles after the start of the first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, the ADC Interrupt Flag (ADIF) is set,
and ADSC is cleared simultaneously. The software may then set ADSC again, and a new con-
version will be initiated on the first rising ADC clock edge.
ATmega4HVD/8HVD
91