ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 89

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

ATmega4HVD/8HVD
• Bit 2 – OCFnB: Output Compare Flag n B
The OCFnB bit is set when a Compare Match occurs between the Timer/Counter and the data
in OCRnB – Output Compare Register n B. OCFnB is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCFnB is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIEnB (Timer/Counter Compare B Match Interrupt
Enable), and OCFnB are set, the Timer/Counter Compare Match Interrupt is executed.
The OCFnB is not set in 16-bit Output Compare mode when the Output Compare Register
OCRnB is used as the high byte of the 16-bit Output Compare Register or in 16-bit Input Cap-
ture mode when the Output Compare Register OCRnB is used as the high byte of the Input
Capture Register.
• Bit 1– OCFnA: Output Compare Flag n A
The OCFnA bit is set when a Compare Match occurs between the Timer/Counter n and the
data in OCRnA – Output Compare Register n. OCFnA is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCFnA is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIEnA (Timer/Counter n Compare Match Interrupt
Enable), and OCFnA are set, the Timer/Counter n Compare Match Interrupt is executed.
The OCFnA is also set in 16-bit mode when a Compare Match occurs between the
Timer/Counter n and 16-bit data in OCRnB/A. The OCFnA is not set in Input Capture mode
when the Output Compare Register OCRnA is used as an Input Capture Register.
• Bit 0 – TOVn: Timer/Counter n Overflow Flag
The bit TOVn is set when an overflow occurs in Timer/Counter n. TOVn is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOVn is
cleared by writing a logic one to the flag. When the SREG I-bit, TOIEn (Timer/Counter n Over-
flow Interrupt Enable), and TOVn are set, the Timer/Counter n Overflow interrupt is executed.
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