ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 88
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
ATMEGA8HVD-4MX
Manufacturer Part Number
ATMEGA8HVD-4MX
Description
MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8HVD-4MX.pdf
(168 pages)
Specifications of ATMEGA8HVD-4MX
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.4 V
Data Converters
A/D 1x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
18-MLF® Exposed Pad (Staggered Leads), DFN
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
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16.10.6
16.10.7
88
ATmega4HVD/8HVD
TIMSKn – Timer/Counter n Interrupt Mask Register
TIFRn – Timer/Counter n Interrupt Flag Register
In 16-bit mode the OCRnB register contains the high byte of the 16-bit Output Compare Reg-
ister. To ensure that both the high and the low bytes are written simultaneously when the CPU
writes to these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See
Registers in 16-bit Mode” on page
• Bit 3 – ICIEn: Timer/Counter n Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter n Input Capture interrupt is enabled. The corresponding Interrupt
Vector
set.
• Bit 2 – OCIEnB: Timer/Counter n Output Compare Match B Interrupt Enable
When the OCIEnB bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter occurs, i.e., when the OCFnB bit is set in the
Timer/Counter Interrupt Flag Register – TIFRn.
• Bit 1 – OCIEnA: Timer/Counter n Output Compare Match A Interrupt Enable
When the OCIEnA bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter n Compare Match A interrupt is enabled. The corresponding interrupt is exe-
cuted if a Compare Match in Timer/Counter n occurs, i.e., when the OCFnA bit is set in the
Timer/Counter n Interrupt Flag Register – TIFRn.
• Bit 0 – TOIEn: Timer/Counter n Overflow Interrupt Enable
When the TOIEn bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter n Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter n occurs, i.e., when the TOVn bit is set in the Timer/Counter n Inter-
rupt Flag Register – TIFRn.
• Bits 3 – ICFn: Timer/Counter n Input Capture Flag
This flag is set when a capture event occurs, according to the setting of ICENn, ICESn and
ICSn bits in the TCCRnA Register.
ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alterna-
tively, ICFn can be cleared by writing a logic one to its bit location.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(See Section “11.” on page
R
R
7
0
7
0
-
-
R
R
6
0
6
0
-
-
R
R
82.
5
0
5
0
-
-
51.) is executed when the ICFn flag, located in TIFRn, is
R
R
4
0
4
0
-
-
ICIEn
ICFn
R/W
R/W
3
0
3
0
OCIEnB
OCFnB
R/W
R/W
2
0
2
0
OCIEnA
OCFnA
R/W
R/W
1
0
1
0
TOIEn
TOVn
R/W
R
0
0
0
0
8052B–AVR–09/08
”Accessing
TIMSKn
TIFRn
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