ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 97

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

17.8
17.8.1
8052B–AVR–09/08
Register Description
ADCSRA – ADC Control and Status Register A
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
Write this bit to one to start each conversion. The first conversion after ADSC has been written
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is
enabled, will take 27 ADC clock cycles. The conversion time will then be 13 ADC cycles if
ADTEMP is set to zero, or 27 ADC cycles if ADTEMP is set to one. This first conversion per-
forms initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is com-
plete, it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – RES: Reserved bits
These bits are reserved, and will always read as zero.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated. The
ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ADIF is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-
Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI
and CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete
Interrupt is activated.
• Bit 2 – RES: Reserved bit
This bit isreserved, and will always read as zero.
• Bit 1:0 – ADMUX1:0: ADC Channel Selection Bits
These bits selects the analog input that should be connected to the ADC according to
17-3. If these bits are changed during a conversion, the change will not be effective until the
conversion is complete.
Bit
Read/Write
Initial Value
ADEN
R/W
7
0
ADSC
R/W
6
0
R
5
0
-
ADIF
R/W
4
0
ADIE
R/W
3
0
ATmega4HVD/8HVD
R
2
0
-
ADMUX1
R/W
1
0
ADMUX0
R/W
0
0
ADCSRA
Table
97