MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 101

• Manufacturer Part Number: MC68HC16Z1CFC16
• Description: IC MPU 1K RAM 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CFC16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

4.14.1.1 IPIPE0/IPIPE1 Multiplexing
4.14.1.2 Combining Opcode Tracking with Other Capabilities
4.14.2 Breakpoints
M68HC16 Z SERIES
USER’S MANUAL
Six types of information are required to track pipeline activity. To generate the six state
signals, eight pipeline states are encoded and multiplexed into IPIPE0 and IPIPE1.
The multiplexed signals have two phases. State signals are active low.
shows the encoding scheme.
IPIPE0 and IPIPE1 are timed so that a logic analyzer can capture all six pipeline state
signals and address, data, or control bus state in any single bus cycle. Refer to
PENDIX A ELECTRICAL CHARACTERISTICS
State signals can be latched asynchronously on the falling and rising edges of either
address strobe (AS) or data strobe (DS). They can also be latched synchronously us-
ing the microcontroller CLKOUT signal. Refer to the CPU16 Reference Manual
(CPU16RM/AD) for more information on the CLKOUT signal, state signals, and state
signal demux logic.
Pipeline state signals are useful during normal instruction execution and execution of
exception handlers. The signals provide a complete model of the pipeline up to the
point a breakpoint is acknowledged.
Breakpoints are acknowledged after an instruction has executed, when it is in pipeline
stage C. A breakpoint can initiate either exception processing or background debug
mode. IPIPE0/IPIPE1 are not usable when the CPU16 is in background debug mode.
Breakpoints are set by assertion of the microcontroller BKPT pin. The CPU16 supports
breakpoints on any memory access. Acknowledged breakpoints can initiate either ex-
ception processing or background debug mode. After BDM has been enabled, the
CPU16 will enter BDM when the BKPT input is asserted.
• If BKPT assertion is synchronized with an instruction prefetch, the instruction is
• If BKPT assertion is synchronized with an operand fetch, breakpoint processing
tagged with the breakpoint when it enters the pipeline, and the breakpoint occurs
after the instruction executes.
occurs at the end of the instruction during which BKPT is latched.
Phase
1
2
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 4-6 IPIPE0/IPIPE1 Encoding
IPIPE1 State
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
0
0
1
1
0
0
1
1
IPIPE0 State
0
1
0
1
0
1
0
1
for specifications.
START and FETCH
State Signal Name
EXCEPTION
ADVANCE
INVALID
FETCH
START
NULL
NULL
Table 4-6
AP-
4-41