MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 167

• Manufacturer Part Number: MC68HC16Z1CFC16
• Description: IC MPU 1K RAM 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CFC16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

5.8.5 Interrupt Acknowledge Bus Cycles
5.9 Chip-Selects
M68HC16 Z SERIES
USER’S MANUAL
Interrupt acknowledge bus cycles are CPU space cycles that are generated during ex-
ception processing. For further information about the types of interrupt acknowledge
bus cycles determined by AVEC or DSACK, refer to
CHARACTERISTICS
Typical microcontrollers require additional hardware to provide external chip-select
signals. The MCU includes 12 programmable chip-select circuits that can provide from
two to 16 clock-cycle access to external memory and peripherals. Address block sizes
of 2 Kbytes to 512 Kbytes can be selected. However, because ADDR[23:20] follow the
state of ADDR19, 512-Kbyte blocks are the largest usable size.
gram of a basic system that uses chip-selects.
D. Modules or external peripherals that have requested interrupt service decode
E. After arbitration, the interrupt acknowledge cycle is completed in one of the fol-
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC and the processor
3. Request priority is latched into the CCR IP field from the address bus.
the priority value in ADDR[3:1]. If request priority is the same as acknowledged
priority, arbitration by IARB contention takes place.
lowing ways:
1. When there is no contention (IARB = %0000), the spurious interrupt monitor
2. The dominant interrupt source supplies a vector number and DSACK sig-
3. The AVEC signal is asserted (the signal can be asserted by the dominant
4. The bus monitor asserts BERR and the CPU16 generates the spurious in-
transfers control to the exception handler routine.
asserts BERR, and the CPU16 generates the spurious interrupt vector
number.
nals appropriate to the access. The CPU16 acquires the vector number.
interrupt source or the pin can be tied low), and the CPU16 generates an
autovector number corresponding to interrupt priority.
terrupt vector number.
Freescale Semiconductor, Inc.
For More Information On This Product,
and the SIM Reference Manual (SIMRM/AD).
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
APPENDIX A ELECTRICAL
Figure 5-21
is a dia-
5-61