MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 142

• Manufacturer Part Number: MC68HC16Z1CFC16
• Description: IC MPU 1K RAM 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CFC16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

5.6 Bus Operation
5.6.1 Synchronization to CLKOUT
5-36
Current
NOTES:
Cycle
10
11
12
13
Internal microcontroller modules are typically accessed in two system clock cycles.
Regular external bus cycles use handshaking between the MCU and external periph-
erals to manage transfer size and data. These accesses take three system clock cy-
cles, with no wait states. During regular cycles, wait states can be inserted as needed
by bus control logic. Refer to
Fast-termination cycles, which are two-cycle external accesses with no wait states,
use chip-select logic to generate handshaking signals internally. Refer to
Termination Cycles
timing, as well as chip-select signal timing, are specified in
CAL
information about each type of bus cycle.
External devices connected to the MCU bus can operate at a clock frequency different
from the frequencies of the MCU as long as the external devices satisfy the interface
signal timing constraints. Although bus cycles are classified as asynchronous, they are
interpreted relative to the MCU system clock output (CLKOUT).
1
2
3
4
5
6
7
8
9
1. Operands in parentheses are ignored by the CPU16 during read cycles.
2. The CPU16 treats misaligned long-word transfers as two misaligned-word transfers.
3. Three byte transfer cases occur only as a result of an aligned long word to 8-bit port transfer.
CHARACTERISTICS. Refer to the SIM Reference Manual (SIMRM/AD) for more
Byte to 16-bit port (even)
Byte to 8-bit port (even)
Byte to 16-bit port (odd)
Long word to 16-bit port
Long word to 16-bit port
Three byte to 8-bit port
Byte to 8-bit port (odd)
Long word to 8-bit port
Long word to 8-bit port
Word to 16-bit port
Word to 16-bit port
Word to 8-bit port
Word to 8-bit port
Transfer Case
(misaligned)
(misaligned)
(misaligned)
(misaligned)
(aligned)
(aligned)
(aligned)
(aligned)
2
2
Freescale Semiconductor, Inc.
and
For More Information On This Product,
3
Table 5-16 Operand Alignment
SYSTEM INTEGRATION MODULE
5.9 Chip-Selects
SIZ1
0
0
0
0
1
1
1
1
0
1
0
1
1
5.6.2 Regular Bus Cycle
Go to: www.freescale.com
SIZ0
1
1
1
1
0
0
0
0
0
0
0
0
1
ADDR0 DSACK1 DSACK0
0
1
0
1
0
1
0
1
0
1
0
1
1
for more information. Bus control signal
1
1
0
0
1
1
0
0
1
1
0
0
1
for more information.
0
0
1
1
0
0
1
1
0
0
1
1
0
APPENDIX A ELECTRI-
DATA
[15:8]
(OP0)
(OP0)
(OP0)
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
M68HC16 Z SERIES
USER’S MANUAL
(OP0)
DATA
(OP0)
(OP0)
(OP1)
(OP0)
(OP1)
(OP0)
(OP0)
[7:0]
OP0
OP1
OP0
OP1
OP0
5.6.3 Fast
1
Cycle
Next
13
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—
—
—
—
2
1
3
1
7
3
5