MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 393

• Manufacturer Part Number: MC68HC16Z1CFC16
• Description: IC MPU 1K RAM 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CFC16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

MODE — Asynchronous/Synchronous Mode
BYTE[1:0] — Upper/Lower Byte Option
R/W[1:0]— Read/Write
STRB — Address Strobe/Data Strobe
DSACK[3:0] — Data Strobe Acknowledge
M68HC16 Z SERIES
USER’S MANUAL
CSORBT and CSOR[0:10] contain parameters that support operations from external
memory devices. Bit and field definitions for CSORBT and CSOR[0:10] are the same.
In asynchronous mode, chip-select assertion is synchronized with AS and DS.
In synchronous mode, the chip-select signal is asserted with ECLK.
This field is used only when the chip-select 16-bit port option is selected in the pin as-
signment register. This allows the usage of two external 8-bit memory devices to be
concatenated to form a 16-bit memory.
This field causes a chip-select to be asserted only for a read, only for a write, or for
both read and write.
This bit controls the timing for assertion of a chip-select in asynchronous mode only.
Selecting address strobe causes the chip-select to be asserted synchronized with ad-
dress strobe. Selecting data strobe causes the chip-select to be asserted synchro-
nized with data strobe. Data strobe timing is used to create a write strobe when
needed.
This field specifies the source of DSACK in asynchronous mode as internally generat-
ed or externally supplied. It also allows the user to adjust bus timing with internal
DSACK generation by controlling the number of wait states that are inserted to opti-
mize bus speed in a particular application.
coding. The fast termination encoding (%1110) effectively corresponds to –1 wait
states.
0 = Asynchronous mode is selected.
1 = Synchronous mode is selected, and used with ECLK peripherals.
0 = Address strobe
1 = Data strobe
Table D-14 Read/Write Field Bit Encoding
Freescale Semiconductor, Inc.
Table D-14
Table D-13 BYTE Field Bit Encoding
For More Information On This Product,
BYTE[1:0]
R/W[1:0]
00
01
10
11
00
01
10
11
Go to: www.freescale.com
REGISTER SUMMARY
shows the options.
Table D-13
Description
Description
Table D-15
Read/Write
Lower byte
Upper byte
Both bytes
Read only
Write only
Disable
Disable
shows upper/lower byte options.
shows the DSACK[3:0] field en-
D-19