MC912D60ACPV8 Freescale Semiconductor, MC912D60ACPV8 Datasheet - Page 105

• Manufacturer Part Number: MC912D60ACPV8
• Description: IC MCU 6K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60ACPV8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Technical Data — MC68HC912D60A
8.1 Contents
8.2 Introduction
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
8.2
8.3
8.4
8.5
8.6
8.7
8.8
The MC68HC912D60A EEPROM nonvolatile memory is arranged in a
16-bit configuration. The EEPROM array may be read as either bytes,
aligned words or misaligned words. Access times are one bus cycle for
byte and aligned word access and two bus cycles for misaligned word
operations.
Programming is by byte or aligned word. Attempts to program or erase
misaligned words will fail. Only the lower byte will be latched and
programmed or erased. Programming and erasing of the user EEPROM
can be done in normal modes.
Each EEPROM byte or aligned word must be erased before
programming. The EEPROM module supports byte, aligned word, row
(32 bytes) or bulk erase, all using the internal charge pump. The erased
state is $FF. The EEPROM module has hardware interlocks which
protect stored data from corruption by accidentally enabling the
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
EEPROM Selective Write More Zeros . . . . . . . . . . . . . . . . . . 106
EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .107
EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Program/Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Programming EEDIVH and EEDIVL Registers. . . . . . . . . . . . 116
Shadow Word Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
EEPROM Memory
Section 8. EEPROM Memory
Technical Data
105