MC912D60ACPV8 Freescale Semiconductor, MC912D60ACPV8 Datasheet - Page 119

• Manufacturer Part Number: MC912D60ACPV8
• Description: IC MCU 6K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60ACPV8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Technical Data — MC68HC912D60A
9.1 Contents
9.2 Introduction
9.2.1 Exception Priority
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
CPU12 exceptions include resets and interrupts. Each exception has an
associated 16-bit vector, which points to the memory location where the
routine that handles the exception is located. Vectors are stored in the
upper 128 bytes of the standard 64K byte address map.
The six highest vector addresses are used for resets and non-maskable
interrupt sources. The remainder of the vectors are used for maskable
interrupts, and all must be initialized to point to the address of the
appropriate service routine.
A hardware priority hierarchy determines which reset or interrupt is
serviced first when simultaneous requests are made. Six sources are not
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Interrupt Control and Priority Registers . . . . . . . . . . . . . . . . . 123
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Resets and Interrupts
Section 9. Resets and Interrupts
Technical Data
119