MC912D60ACPV8 Freescale Semiconductor, MC912D60ACPV8 Datasheet - Page 154
MC912D60ACPV8
Manufacturer Part Number
MC912D60ACPV8
Description
IC MCU 6K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet
1.MC912D60ACFUE8.pdf
(460 pages)
Specifications of MC912D60ACPV8
Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
68
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Clock Functions
11.6.11 Pseudo-STOP exit without Limp Home mode, clock monitor enabled
11.6.12 Pseudo-STOP exit without Limp Home mode, clock monitor disabled
11.6.13
11.6.14 Summary of STOP and pseudo-STOP Mode Exit Conditions
Technical Data
154
CAUTION:
(NOLHM=1, CME=1, DLY=X)
If the NOLHM bit is set and the CME (or FCME) bits are set, a clock
monitor failure is detected when a STOP instruction is executed and the
MCU resets via the clock monitor reset vector.
(NOLHM=1, CME=0, DLY=1)
If NOLHM is set to 1 and the CME and FCME bits are cleared, the limp
home clock is not used. In this mode, crystal activity is the only method
by which the device may recover from Pseudo-STOP. The device will
start execution with the EXTALi clock following 4096 XCLK cycles.
(NOLHM=1, CME=0, DLY=0)
If NOLHM is set to 1 and the CME and FCME bits are cleared, the limp
home clock is not used. In this mode, crystal activity is the only method
by which the device may recover from Pseudo-STOP. The device will
start execution with the EXTALi clock following 16 XCLK cycles.
Due to switching of the clock this configuration is not recommended.
Table 11-1
and pseudo-STOP modes using Interrupt, Key-interrupt and XIRQ.
A short RESET pulse should not be used to exit stop or pseudo-STOP
mode because Limp Home mode is automatically entered after RESET
(when V
oscillator startup time (as in power on reset) in order to remove the risk
of code runaway.
DDPLL
and
=V
Table 11-2
DD
Clock Functions
). The RESET wakeup pulse must be longer than the
summarise the exit conditions from STOP
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
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