MPC5553MZQ132 Freescale Semiconductor, MPC5553MZQ132 Datasheet - Page 45

IC MCU MPC5553 REV A 324-PBGA

MPC5553MZQ132

Manufacturer Part Number
MPC5553MZQ132
Description
IC MCU MPC5553 REV A 324-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC55xx Qorivvar
Datasheet

Specifications of MPC5553MZQ132

Core Processor
e200z6
Core Size
32-Bit
Speed
132MHz
Connectivity
CAN, EBI/EMI, Ethernet, SCI, SPI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
220
Program Memory Size
1.5MB (1.5M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.65 V
Data Converters
A/D 40x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
324-PBGA
Processor Series
MPC5xxx
Core
e200z6
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
7-Wire, DSPI, ESCI
Maximum Clock Frequency
132 MHz
Number Of Timers
56
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
For Use With
MPC5553EVBISYS - KIT EVAL ISYSTEMS MPC5553MPC5553EVBGHS - KIT EVAL GREEN HILLS SOFTWAREMPC5553EVB - KIT EVAL MPC5553MZP132MPC5553EVBE - BOARD EVAL FOR MPC5553
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC5553MZQ132
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC5553MZQ132
Quantity:
20
3.14
Media Independent Interface (MII) Fast Ethernet Controller (FEC) signals use transistor-to-transistor logic
(TTL) signal levels compatible with devices operating at 3.3 V. The timing specifications for the MII FEC
signals are independent of the system clock frequency (part speed designation).
3.14.1
The receive functions correctly up to an FEC_RX_CLK maximum frequency of 25 MHz plus one percent.
There is no minimum frequency requirement. The processor clock frequency must exceed four times the
FEC_RX_CLK frequency.
Table 28
Figure 28
Freescale Semiconductor
Spec
1
2
3
4
FEC_RXD[3:0] (inputs)
FEC_RX_CLK (input)
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
FEC_RX_CLK pulse-width high
FEC_RX_CLK pulse-width low
lists MII FEC receive channel timings.
Fast Ethernet AC Timing Specifications
shows MII FEC receive signal timings listed in
MII FEC Receive Signal Timing
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and FEC_RX_CLK
FEC_RX_ER
FEC_RX_DV
Figure 28. MII FEC Receive Signal Timing Diagram
Characteristic
MPC5553 Microcontroller Data Sheet, Rev. 3.0
Table 28. MII FEC Receive Signal Timing
1
2
3
Table
28.
4
Min.
35%
35%
5
5
65%
65%
Max
Electrical Characteristics
FEC_RX_CLK period
FEC_RX_CLK period
Unit
ns
ns
45

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