MPC5553MZQ132 Freescale Semiconductor, MPC5553MZQ132 Datasheet - Page 66

• Manufacturer Part Number: MPC5553MZQ132
• Description: IC MCU MPC5553 REV A 324-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC55xx Qorivvar

Specifications of MPC5553MZQ132

• Core Processor: e200z6
• Core Size: 32-Bit
• Speed: 132MHz
• Connectivity: CAN, EBI/EMI, Ethernet, SCI, SPI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 220
• Program Memory Size: 1.5MB (1.5M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.65 V
• Data Converters: A/D 40x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC5xxx
• Core: e200z6
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 7-Wire, DSPI, ESCI
• Maximum Clock Frequency: 132 MHz
• Number Of Timers: 56
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: MPC5553EVBISYS - KIT EVAL ISYSTEMS MPC5553MPC5553EVBGHS - KIT EVAL GREEN HILLS SOFTWAREMPC5553EVB - KIT EVAL MPC5553MZP132MPC5553EVBE - BOARD EVAL FOR MPC5553
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Revision History for the MPC5553 Data Sheet
66
Table 25
Figure 17
Table 26
Table 27
Section 3.14, “Fast Ethernet AC Timing
Figure 32
Figure 33
Figure 34
Location
eMIOS Timing:
EQADC SSI Timing Characteristics:
DSPI Timing:
Added eMIOS Timing figure.
MPC5553 208 Package: Deleted the version number and date.
MPC5553 324 Package: Deleted the version number and date.
and
Removed the ‘M’ in the diagram labels that refer to the specification numbers.
• Deleted (MTS) from the heading, table, and footnotes.
• Footnote 1, changed ‘V
• Footnote 1: Deleted ‘F
• Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
• Footnote 1, changed ‘V
• Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum
• Spec 1: SCK cycle time; Changed 80 MHz = 24.4, and 112 MHz = 17.5.
• Footnote 1: Changed to read: ‘All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type
• Footnote 1, changed ‘V
• Deleted from table title ‘(Pads at 3.3 V or 5.0 V)’
• Deleted 1st line in table ‘CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.’
• Spec 1: FCK frequency -- removed.
• Combined footnotes 1 and 2, and moved the new footnote to Spec 2. Moved old footnote 3 that is now
• Footnote 1, deleted ‘V
• Footnote 2: added ‘cycle’ after ‘duty’ to read: FCK duty cycle is not 50% when . . . .
‘ and CL = 200 pF with SRC = 0b11.’
eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM;
114 MHz parts allow for 112 MHz system clock + 2% FM, and 132 MHz parts allow for 128 MHz system clock +
2% FM.
M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew rate.’ Deleted
‘V
footnote 2 to Spec 2.
Changed ‘CL = 50 pF’ to ‘CL = 25 pF.’
Figure 35
DD
Table 33. Table and Figure Changes Between Rev. 2.0 and 3.0 (continued)
= 1.35–1.65 V’ and ‘V
MPC5553 416 Package: Deleted the version number and date.
DD
SYS
DDEH
DDEH
DDEH
MPC5553 Microcontroller Data Sheet, Rev. 3.0
Specifications” :
= 1.35–1.65 V’ and ‘V
= 132 MHz’, ‘V
DD33
= 4.5–5.5;’ to ‘V
= 4.5–5.5;’ to ‘V
= 4.5–5.5;’ to ‘V
and V
DDSYN
Description of Changes
DD
Figure
= 1.35–1.65 V’, ‘V
DDEH
DDEH
DDEH
= 3.0–3.6 V.
DD33
28,
= 4.5–5.25;’
= 4.5–5.25;’
= 4.5–5.25;’
and V
Figure
DDSYN
29,
DD33
Figure
= 3.0–3.6V.’
and V
30, and
DDSYN
Figure
= 3.0–3.6 V’ and
31.
Freescale Semiconductor