SAF-XC167CI-32F20F BB-A Infineon Technologies, SAF-XC167CI-32F20F BB-A Datasheet - Page 18
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SAF-XC167CI-32F20F BB-A
Manufacturer Part Number
SAF-XC167CI-32F20F BB-A
Description
IC MCU 16BIT 256KB TQFP-144-19
Manufacturer
Infineon Technologies
Series
XC16xr
Datasheet
1.SAF-XC167CI-32F20F_BB-A.pdf
(90 pages)
Specifications of SAF-XC167CI-32F20F BB-A
Core Processor
C166SV2
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.7 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
For Use With
B158-H8963-X-X-7600IN - KIT EASY XC167CIMCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
FX167CI32F20FBBANT
FX167CI32F20FBBAXT
SAFXC167CI32F20FBBAT
SP000098776
SP000224700
FX167CI32F20FBBAXT
SAFXC167CI32F20FBBAT
SP000098776
SP000224700
Table 2
Sym-
bol
P20
P20.0
P20.1
P20.2
P20.4
P20.5
P20.12
Data Sheet
Pin
Num.
90
91
92
93
94
3
Pin Definitions and Functions (cont’d)
Input
Outp.
IO
O
O
I
O
I
O
Function
Port 20 is a 6-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output. The input threshold of Port 20 is selectable
(standard or special).
The following Port 20 pins also serve for alternate functions:
RD
WR/WRL
READY
ALE
EA
RSTOUT
Note: Port 20 pins may input configuration values (see EA).
External Memory Read Strobe, activated for
every external instruction or data read access.
External Memory Write Strobe.
In WR-mode this pin is activated for every
external data write access.
In WRL-mode this pin is activated for low byte
data write accesses on a 16-bit bus, and for
every data write access on an 8-bit bus.
READY Input. When the READY function is
enabled, memory cycle time waitstates can be
forced via this pin during an external access.
Address Latch Enable Output.
Can be used for latching the address into
external memory or an address latch in the
multiplexed bus modes.
External Access Enable pin.
A low-level at this pin during and after Reset
forces the XC167 to latch the configuration from
PORT0 and pin RD, and to begin instruction
execution out of external memory.
A high-level forces the XC167 to latch the
configuration from pins RD, ALE, and WR, and
to begin instruction execution out of the internal
program memory. “ROMless” versions must
have this pin tied to ‘0’.
Internal Reset Indication Output.
Is activated asynchronously with an external
hardware reset. It may also be activated
(selectable) synchronously with an internal
software or watchdog reset.
Is deactivated upon the execution of the EINIT
instruction, optionally at the end of reset, or at
any time (before EINIT) via user software.
16
General Device Information
XC167CI-32F
Derivatives
V1.1, 2006-08