SAF-XC167CI-32F20F BB-A Infineon Technologies, SAF-XC167CI-32F20F BB-A Datasheet - Page 78
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SAF-XC167CI-32F20F BB-A
Manufacturer Part Number
SAF-XC167CI-32F20F BB-A
Description
IC MCU 16BIT 256KB TQFP-144-19
Manufacturer
Infineon Technologies
Series
XC16xr
Datasheet
1.SAF-XC167CI-32F20F_BB-A.pdf
(90 pages)
Specifications of SAF-XC167CI-32F20F BB-A
Core Processor
C166SV2
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.7 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
For Use With
B158-H8963-X-X-7600IN - KIT EASY XC167CIMCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
FX167CI32F20FBBANT
FX167CI32F20FBBAXT
SAFXC167CI32F20FBBAT
SP000098776
SP000224700
FX167CI32F20FBBAXT
SAFXC167CI32F20FBBAT
SP000098776
SP000224700
Variable Memory Cycles
External bus cycles of the XC167 are executed in five subsequent cycle phases (AB, C,
D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
The duration of the access phase can optionally be controlled by the external module via
the READY handshake input.
This table provides a summary of the phases and the respective choices for their
duration.
Table 21
Bus Cycle Phase
Address setup phase, the standard duration of this
phase (1 … 2 TCP) can be extended by 0 … 3 TCP
if the address window is changed
Command delay phase
Write Data setup/MUX Tristate phase
Access phase
Address/Write Data hold phase
Note: The bandwidth of a parameter (minimum and maximum value) covers the whole
Data Sheet
operating range (temperature, voltage) as well as process variations. Within a
given device, however, this bandwidth is smaller than the specified range. This is
also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
Programmable Bus Cycle Phases (see timing diagrams)
76
Parameter Valid Values Unit
tp
tp
tp
tp
tp
AB
C
D
E
F
Electrical Parameters
1 … 2 (5)
0 … 3
0 … 1
1 … 32
0 … 3
XC167CI-32F
Derivatives
V1.1, 2006-08
TCP
TCP
TCP
TCP
TCP