SAK-XC161CS-32F40F BB-A Infineon Technologies, SAK-XC161CS-32F40F BB-A Datasheet - Page 24

• Manufacturer Part Number: SAK-XC161CS-32F40F BB-A
• Description: IC MCU 16BIT 256KB TQFP-144-19
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAK-XC161CS-32F40F BB-A

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 99
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 12x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, IIC, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 99
• Number Of Timers: 9
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Packages: PG-TQFP-144
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 12.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 12
• Program Memory: 256.0 KByte
• For Use With: MCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: KX161CS32F40FBBANT; KX161CS32F40FBBAXT; SAKXC161CS32F40FBBAT; SP000098775; SP000224544

4) The Emulation PSRAM (EPSRAM) realizes a 2
5) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
3.2
All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes
are as follows:
•
•
•
•
In the demultiplexed bus modes, addresses are output on PORT1 and data is
input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both
addresses and data use PORT0 for input/output. The high order address (segment) lines
use Port 4. The number of active segment address lines is selectable, restricting the
external address space to 8 Mbytes … 64 Kbytes. This is required when interface lines
are assigned to Port 4.
Up to 5 external CS signals (4 windows plus default) can be generated in order to save
external glue logic. External modules can directly be connected to the common
address/data bus and their individual select lines.
Access to very slow memories or modules with varying access times is supported via a
particular ‘Ready’ function. The active level of the control input signal is selectable.
A HOLD/HLDA protocol is available for bus arbitration and allows the sharing of external
resources with other bus masters. The bus arbitration is enabled by software. After
enabling, pins P6.7 … P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the
EBC. In Master Mode (default after reset) the HLDA pin is an output. In Slave Mode pin
HLDA is switched to input. This allows the direct connection of the slave controller to
another master controller without glue logic.
Important timing characteristics of the external bus interface have been made
programmable (via registers TCONCSx/FCONCSx) to allow the user the adaption of a
wide range of different types of memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via registers
ADDRSELx) which control the access to different resources with different bus
characteristics. These address windows are arranged hierarchically where window 4
overrides window 3, and window 2 overrides window 1. All accesses to locations not
1) Bus modes are switched dynamically if several address windows with different mode settings are used.
Data Sheet
peripherals properly.
16 … 24-bit Addresses, 16-bit Data, Demultiplexed
16 … 24-bit Addresses, 16-bit Data, Multiplexed
16 … 24-bit Addresses, 8-bit Data, Multiplexed
16 … 24-bit Addresses, 8-bit Data, Demultiplexed
External Bus Controller
nd
access path to the PSRAM with a different timing.
22
Functional Description
XC161CS-32F
Derivatives
V1.2, 2006-08
1)
, which