DSP56311VL150 Freescale Semiconductor, DSP56311VL150 Datasheet - Page 27

• Manufacturer Part Number: DSP56311VL150
• Description: IC DSP 24BIT FIXED POINT 196-BGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56311VL150

• Interface: Host Interface, SSI, SCI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 384kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Package: 196MA-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 150 MHz
• Ram Size: 384 KB
• Device Million Instructions Per Second: 150 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.4.4
Freescale Semiconductor
No.
10
13
14
15
16
17
18
19
20
21
24
25
8
9
Delay from RESET assertion to all pins at reset value
Required RESET duration
•
•
•
•
•
•
Delay from asynchronous RESET deassertion to first external address
output (internal reset deassertion)
•
•
Mode select set-up time
Mode select hold time
Minimum edge-triggered interrupt request assertion width
Minimum edge-triggered interrupt request deassertion width
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external
memory access address out valid
•
•
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-
purpose transfer output valid caused by first interrupt instruction
execution
Delay from address output valid caused by first interrupt instruction
execute to interrupt request deassertion for level sensitive fast
interrupts
Delay from RD assertion to interrupt request deassertion for level
sensitive fast interrupts
Delay from WR assertion to interrupt request deassertion for level
sensitive fast interrupts
•
•
•
•
Duration for IRQA assertion to recover from Stop state
Delay from IRQA assertion to fetch of first instruction (when exiting
Stop)
•
•
•
Power on, external clock generator, PLL disabled
Power on, external clock generator, PLL enabled
Power on, internal oscillator
During STOP, XTAL disabled (PCTL Bit 16 = 0)
During STOP, XTAL enabled (PCTL Bit 16 = 1)
During normal operation
Minimum
Maximum
Caused by first interrupt instruction fetch
Caused by first interrupt instruction execution
DRAM for all WS
SRAM WS = 1
SRAM WS = 2, 3
SRAM WS ≥ 4
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is
enabled
(Operating Mode Register Bit 6 = 0)
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is
not enabled (Operating Mode Register Bit 6 = 1)
PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop
Delay)
Reset, Stop, Mode Select, and Interrupt Timing
2, 3
1, 7, 8
Table 2-7.
1, 7, 8
1, 7, 8
Characteristics
4
5
Reset, Stop, Mode Select, and Interrupt Timing
DSP56311 Technical Data, Rev. 8
3
PLC × ET
PLC × ET
(WS + 3.75) × T
(WS + 3.25) × T
(WS + 3.5) × T
(WS + 3.5) × T
(WS + 2.5) × T
(WS + 3) × T
(8.25 ± 0.5) × T
20.25 × T
3.25 × T
4.25 × T
7.25 × T
Expression
10 × T
75000 × ET
75000 × ET
PLC/2) × T
1000 × ET
Maximum:
Maximum:
Maximum:
Minimum:
Minimum:
Minimum:
50 × ET
C
0.5) × T
C
2.5 × T
2.5 × T
× PDF + (128 K −
× PDF + (23.75 ±
—
C
C
C
C
C
+ 5.0
C
+ 2.0
+ 2.0
+ 2.0
C
C
C
C
C
C
C
C
C
+ 10
– 10.94
C
– 10.94
– 10.94
– 10.94
C
C
C
– 10.94
– 10.94
C
AC Electrical Characteristics
6
232.5 ns
333.3
Min
6.67
0.50
0.50
16.7
16.7
23.7
30.0
30.4
51.0
72.0
51.7
0.0
6.6
6.6
5.9
1.3
—
—
—
—
—
—
—
—
150 MHz
12.3 ms
Note 8
Note 8
Note 8
Note 8
Note 8
Note 8
145.0
Max
26.0
58.3
9.1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ms
ms
ms
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-7