MCF5216CVF66 Freescale Semiconductor, MCF5216CVF66 Datasheet - Page 746

• Manufacturer Part Number: MCF5216CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5216CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 256
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Revision History
B-10
Figure 17-26/Page
Figure 23-18/Page
25.5.8/Page 25-25
Table 17-11/Page
Table 25-17/Page
Table 25-17/Page
17.4.6/Page 17-7
Table 17-9/Page
23.5.1.2.2/Page
20.5.13/Page
Location
Section
Section
Section
Section
17-17
17-19
17-41
20-12
23-18
23-19
25-29
25-27
Add the following subsection entitled “Duplicate Frame Transmission”:
The FEC fetches transmit buffer descriptors (TxBDs) and the corresponding transmit data continuously
until the transmit FIFO is full. It does not determine whether the TxBD to be fetched is already being
processed internally (as a result of a wrap). As the FEC nears the end of the transmission of one frame,
it begins to DMA the data for the next frame. In order to remain one BD ahead of the DMA, it also fetches
the TxBD for the next frame. It is possible that the FEC will fetch from memory a BD that has already been
processed but not yet written back (that is, it is read a second time with the R bit still set). In this case, the
data is fetched and transmitted again.
Using at least three TxBDs fixes this problem for large frames, but not for small frames. To ensure correct
operation for either large or small frames, one of the following must be true:
Correct MIB block counters end addresses to IPSBAR + 0x12FF.
Add RMON_R_DROP with an IPSBAR Offset of 0x1280 and a description of ‘Count of frames not
Change EMRBR register address from “IPSBAR + 0x11B8” to “IPSBAR + 0x1188”.
Deleted reference to nonexistent CF bits in the figure and bit descriptions for the GPTFLG2 register.
Remove the two 16-bit divider blocks from timer input, as the divider is not available using external clock
Remove 16-bit divider from equation, as the divider is not available using external clock sources.
Change end of last sentence from “...and can be written by the host to ‘0’.” to “...and can be written by the
Remove the following information from the BITERR and ACKERR descriptions as these fields are read
Change last sentence in ERRINT description from: “To clear this bit, first read it as a one, then write as a
Add the following information to the BOFFINT and WAKEINT descriptions: “To clear this bit, first read it
Definition of bits ERRINT and BOFFINT are incorrect for register ESTAT: ERRINT should be bit 1,
• The FEC software driver ensures that there is always at least one TxBD with the ready bit cleared.
• Every frame uses more than one TxBD and every TxBD but the last is written back immediately after
• The FEC software driver ensures a minimum frame size, n. The minimum number of TxBDs is then
the data is fetched.
(Tx FIFO Size ÷ (n + 4)) rounded up to the nearest integer (though the result cannot be less than
three). The default Tx FIFO size is 192 bytes; this size is programmable.
counted correctly’.
sources.
host to ‘1’.”
only: “To clear this bit, first read it as a one, then write it as a one. Writing zero has no effect.” (This is
a rescindment of a previous documentation errata.)
zero. Writing a one has no effect.” to “To clear this bit, first read it as a one, then write a one. Writing a
zero has no effect.”
as a one, then write it as a one. Writing zero has no effect.”
BOFFINT should be bit 2. They should be cleared by writing a one instead of a zero.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table B-7. Rev. 2.3 to Rev. 3 Changes (continued)
Description
Freescale Semiconductor