ST16C654IQ64-F Exar Corporation, ST16C654IQ64-F Datasheet - Page 17

• Manufacturer Part Number: ST16C654IQ64-F
• Description: IC UART FIFO 64B QUAD 64LQFP
• Manufacturer: Exar Corporation
• Type: Quad UART with 16-byte FIFOsr

Specifications of ST16C654IQ64-F

• Number Of Channels: 4, QUART
• Package / Case: 64-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS232
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 3 mA to 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 45 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.97 V to 5.5 V
• No. Of Channels: 4
• Uart Features: Infrared (IrDA) Encoder/Decoder
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1273

xr
REV. 5.0.2
F
IGURE
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
11. A
UTO
(RXA FIFO
CTSB#
RXA FIFO
Interrupt)
RTSA#
TXB
INTA
Trigger Reached
RTS
S
Receiver FIFO
Trigger Level
Local UART
ELECTED
Transmitter
Auto CTS
Auto RTS
UARTA
Monitor
AND
L
Data Starts
EVEL
Receive
16
56
60
8
Data
CTS F
T
RIGGER
Assert RTS# to Begin
1
2
Transmission
Trigger Level
3
T
LOW
4
RX FIFO
ABLE
I
RTSA#
TXA
NT
CTSA#
RXA
ON
C
ON
P
ONTROL
7: A
IN
A
16
56
60
8
UTO
CTIVATION
5
O
RTS/CTS F
7
PERATION
Threshold
RTS High
17
6
8
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
D
OFF
Suspend
RTS# P
E
(L
-
OFF
LOW
ASSERTED
OGIC
16
56
60
60
C
RTSB#
1)
CTSB#
IN
RTS Low
Threshold
RXB
ONTROL
TXB
Restart
9
10
11
R
E
RTS# P
(L
Trigger Reached
Remote UART
ON
-
Trigger Level
Receiver FIFO
ASSERTED
OGIC
12
Auto CTS
Transmitter
Auto RTS
UARTB
16
56
Monitor
ON
0
8
0)
IN
Trigger Level
RX FIFO
RTSCTS1
ST16C654/654D