ST16C654IQ64-F Exar Corporation, ST16C654IQ64-F Datasheet - Page 23

• Manufacturer Part Number: ST16C654IQ64-F
• Description: IC UART FIFO 64B QUAD 64LQFP
• Manufacturer: Exar Corporation
• Type: Quad UART with 16-byte FIFOsr

Specifications of ST16C654IQ64-F

• Number Of Channels: 4, QUART
• Package / Case: 64-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS232
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 3 mA to 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 45 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.97 V to 5.5 V
• No. Of Channels: 4
• Uart Features: Infrared (IrDA) Encoder/Decoder
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1273

xr
REV. 5.0.2
A
A2-A0
DDRESS
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
T
ABLE
N
MCR
RHR
MSR
THR
FCR
SPR
DLM
R
LCR
LSR
DLL
IER
ISR
AME
EG
10: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR Divisor
RD/WR
RD/WR
RD/WR
RD/WR
W
R
WR
WR
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
Enabled
Enable
Trigger
Enable
FIFOs
Global
CTS#
Pres-
B
BRG
caler
Error
Input
Bit-7
Bit-7
CD#
Bit-7
Bit-7
Bit-7
Int.
IT
0/
0/
-7
RX FIFO
IR Mode
Enabled
ENable
Enable
Trigger
Set TX
THR &
FIFOs
Empty
RTS#
Break
B
Input
Bit-6
Bit-6
TSR
Bit-6
Bit-6
Bit-6
RI#
Int.
IT
0/
0/
-6
16C550 Compatible Registers
Baud Rate Generator Divisor
TX FIFO
Set Par-
Xoff Int.
XonAny
Source
Enable
Trigger
Empty
DSR#
B
Input
Bit-5
Bit-5
Bit-5
THR
Bit-5
Bit-5
Bit-5
INT
ity
IT
0/
0/
0/
0/
-5
23
TX FIFO
Lopback
Internal
Source
Trigger
Enable
Enable
Break
Sleep
Mode
Parity
CTS#
B
Even
Input
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
INT
RX
IT
0/
0/
0/
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
-4
S
HADED BITS ARE ENABLED WHEN
RX Fram-
INT Out-
ing Error
Stat. Int.
Modem
(OP2#)
Enable
Source
Enable
Enable
Enable
Parity
Mode
B
Delta
DMA
Bit-3
Bit-3
Bit-3
CD#
Bit-3
Bit-3
Bit-3
INT
put
IT
-3
RX Line
(OP1#)
Enable
Source
Reset
Parity
B
FIFO
Rsvd
Delta
Error
Bit-2
Bit-2
Stat.
Bit-2
Stop
Bit-2
Bit-2
Bit-2
INT
Bits
RI#
Int.
RX
TX
IT
-2
Source
Control
Enable
Length
Output
Empty
Reset
DSR#
RTS#
Over-
B
Word
Delta
FIFO
Error
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
RX
RX
run
TX
Int
IT
-1
Control
Enable
Source
Enable
Length
Output
FIFOs
Ready
DTR#
CTS#
EFR B
B
Word
Delta
Bit-0
Bit-0
Data
Bit-0
Bit-0
Data
Bit-0
Bit-0
Bit-0
INT
ST16C654/654D
RX
Int.
RX
IT
-0
IT
LCR ≠ 0xBF
-4=1
LCR[7] = 0
LCR[7] = 0
LCR[7] = 0
LCR[7] = 1
C
OMMENT