ST16C654IQ64-F Exar Corporation, ST16C654IQ64-F Datasheet - Page 22

IC UART FIFO 64B QUAD 64LQFP

ST16C654IQ64-F

Manufacturer Part Number
ST16C654IQ64-F
Description
IC UART FIFO 64B QUAD 64LQFP
Manufacturer
Exar Corporation
Type
Quad UART with 16-byte FIFOsr
Datasheet

Specifications of ST16C654IQ64-F

Number Of Channels
4, QUART
Package / Case
64-LQFP
Features
*
Fifo's
64 Byte
Protocol
RS232
Voltage - Supply
2.97 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
1.5 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.97 V
Supply Current
3 mA to 6 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 45 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.97 V to 5.5 V
No. Of Channels
4
Uart Features
Infrared (IrDA) Encoder/Decoder
Supply Voltage Range
2.97V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1273

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ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
Each UART channel in the 654 has its own set of configuration registers selected by address lines A0, A1 and
A2 with a specific channel selected (See
and
.
3.0 UART INTERNAL REGISTERS
A2,A1,A0 A
Table
X
0
0
0
0
0
1
1
1
1
0
1
1
1
1
0
10.
X X
0 0
0 1
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1 0
0 0
0 1
1 0
1 1
0 0
DDRESSES
T
ABLE
RHR - Receive Holding Register
THR - Transmit Holding Register
DLL - Div Latch Low Byte
DLM - Div Latch High Byte
IER - Interrupt Enable Register
ISR - Interrupt Status Register
FCR - FIFO Control Register
LCR - Line Control Register
MCR - Modem Control Register
LSR - Line Status Register
Reserved
MSR - Modem Status Register
Reserved
SPR - Scratch Pad Register
EFR - Enhanced Function Reg
Xon-1 - Xon Character 1
Xon-2 - Xon Character 2
Xoff-1 - Xoff Character 1
Xoff-2 - Xoff Character 2
FSTAT - FIFO Status Register
9: UART CHANNEL A AND B UART INTERNAL REGISTERS
16C550 C
R
Table 1
EGISTER
E
NHANCED
and
OMPATIBLE
22
Table
R
EGISTERS
R
2). The complete register set is shown on
EGISTERS
R
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
EAD
/W
RITE
LCR[7] = 1, LCR ≠ 0xBF
FSRS# pin is logic 0
LCR = 0xBF
C
LCR[7] = 0
LCR[7] = 0
LCR[7] = 0
xr
OMMENTS
REV. 5.0.2
Table 9

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