ST16C654IQ64-F Exar Corporation, ST16C654IQ64-F Datasheet - Page 24

• Manufacturer Part Number: ST16C654IQ64-F
• Description: IC UART FIFO 64B QUAD 64LQFP
• Manufacturer: Exar Corporation
• Type: Quad UART with 16-byte FIFOsr

Specifications of ST16C654IQ64-F

• Number Of Channels: 4, QUART
• Package / Case: 64-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS232
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 3 mA to 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 45 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.97 V to 5.5 V
• No. Of Channels: 4
• Uart Features: Infrared (IrDA) Encoder/Decoder
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1273

ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
See “Receiver” on page 15.
See “Transmitter” on page 13.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
4.3.1
A
A2-A0
X X X
DDRESS
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
T
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
ABLE
IER versus Receive FIFO Interrupt Mode Operation
XOFF1 RD/WR
XOFF2 RD/WR
FSTAT
XON1 RD/WR
XON2 RD/WR
N
EFR
R
AME
EG
10: INTERNAL REGISTERS DESCRIPTION.
RD/WR
R
W
RD
EAD
RITE
/
RDYD#
Enable
CTS#
B
Auto
Bit-7
Bit-7
Bit-7
Bit-7
RX-
IT
-7
RDYC#
Enable
RTS#
B
Auto
Bit-6
Bit-6
Bit-6
Bit-6
RX-
IT
-6
Enhanced Registers
RDYB#
Special
Select
B
Char
Bit-5
Bit-5
Bit-5
Bit-5
RX-
IT
-5
24
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
RDYA#
Enable
B
Bit-4
Bit-4
Bit-4
Bit-4
RX-
IT
-4
S
HADED BITS ARE ENABLED WHEN
RDYD#
B
Soft-
ware
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Cntl
TX-
IT
-3
RDYC#
B
ware
Soft-
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
TX-
IT
-2
RDYB#
B
Soft-
ware
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Cntl
TX-
IT
-1
RDYA#
EFR B
B
ware
Soft-
Flow
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Cntl
TX-
xr
IT
-0
IT
FSRS# pin is
a logic 0. No
address lines
-4=1
LCR=0
C
REV. 5.0.2
required.
OMMENT
X
BF